JPH06268949A - Flat display device and its drive circuit - Google Patents

Abstract

PURPOSE:To provide an inexpensive flat display device and a drive circuit whose circuit configuration is simple in which excellent display is attained even when inputting video signals with different scanning lines. CONSTITUTION:The display device is provided with a changeover circuit 42 for a 1st mode such as the NTSC system and a 2nd mode for the PAL system, an internal timing pulse generating circuit 24 for 1H period, an thinning window generating circuit 30 providing a signal output invalidating a pulse of 1H period in a timing once for the predetermined number of times so as to make the number of scanning lines for the PAL and NTSC systems equal and a pulse generating circuit 32 generating drive pulses VCK1, VCK2, HST driving a vertical shift register scanning a gate line and a horizontal shift register scanning a signal line based on a pulse from an internal timing pulse generating circuit 24, and in the case of the 2nd mode, the drive pulse from the pulse generating circuit 32 is not inverted or thinned once per the predetermined number of times by the action of a thinning window generating circuit 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device such as a liquid crystal display device and a driving circuit thereof, and more specifically to a number of scanning lines different from the NTSC system such as PAL system or SECAM system. The present invention relates to a flat panel display device and a drive circuit for the flat panel display device capable of displaying a video signal having the above.

[0002]

2. Description of the Related Art For example, N which is the mainstream in Japan and the United States.
In the TSC method, the number of scanning lines is 525. Compared to the PAL method (the number of scanning lines is 625) which is the mainstream in Europe and the like, there is 100 differences in the number of scanning lines, and interlaced scanning is possible. Even in a liquid crystal display device in which dot sequential scanning is performed for each field, there is a difference of about 20%. Therefore, when a PAL video signal is reproduced on a liquid crystal display device having the number of vertical pixels corresponding to the NTSC system, the lower 20% of the screen image area (the number of pixels) is insufficient.

Therefore, in a liquid crystal display device having the same number of pixels in the vertical direction, an NTSC video signal and P
When trying to reproduce an AL video signal, an image in the same range cannot be obtained, and a liquid crystal display device having a corresponding number of vertical pixels has to be used.

As a method for solving such a problem,
For example, as shown in Japanese Unexamined Patent Publication No. 3-21176, when displaying a video signal of a system having a large number of scanning lines on a display device of a system having a small number of scanning lines, the number of scanning lines can be thinned out. Are known.

[0005]

However, in the conventional method of thinning the number of scanning lines in a liquid crystal display device, a driving pulse for driving the liquid crystal display device is generated once, and then the pulse is thinned out. Therefore, there is a problem that the circuit configuration for thinning becomes complicated.

The present invention has been made in view of the above situation, and it is possible to display satisfactorily even when a video signal having a different number of scanning lines is input, such as in the NTSC system and the PAL system or SECAM. It is an object of the present invention to provide a flat panel display device and its driving circuit which have a simple circuit configuration and are inexpensive.

[0007]

In order to achieve the above object, the flat panel display device and its driving device of the present invention drive the flat panel display device in the case of a video signal having a larger number of scanning lines than usual. In the process of generating the drive pulse to
It is characterized in that the drive pulses decimated are generated so that the number of scanning lines becomes pseudo close to the normal number.

Specifically, the flat panel display device of the present invention corresponds to the first number of scanning lines in synchronization with the number of gate lines corresponding to the first number of scanning lines and the scanning of the gate lines. A flat display device comprising at least a signal line to which a video signal is input and arranged so as to be substantially orthogonal to a gate line, and a pixel formed at an intersection of the gate line and the signal line. A first mode in which a video signal corresponding to a second number of scanning lines greater than one scanning line is input, and a second mode in which a video signal corresponding to the first number of scanning lines is input. Mode switching means for switching the mode state, internal timing pulse generating means for generating a pulse of 1H period corresponding to the first scanning line, and the second scanning line number is substantially equal to the first scanning line number. 1 at a given time so that
The pulse for driving the thinning window generating means for outputting the signal for invalidating the pulse of the 1H cycle, the vertical scanning means for scanning the gate line and the horizontal scanning means for scanning the signal line at the timing of Pulse generation means for generating based on the pulse from the internal timing pulse generation means, and in the case of the second mode, the drive pulse generated by the pulse generation means, by the action of the thinning window generation means, It is characterized in that the non-inversion state or the thinning is performed once in the predetermined number of times.

Further, in the driving device of the planar driving device of the present invention, the first mode in which the video signal corresponding to the second scanning line number larger than the first scanning line number is input, and the first scanning With the second mode in which the video signal corresponding to the number of lines is input,
Mode switching means for switching the mode state, internal timing pulse generating means for generating a pulse of 1H period corresponding to the first scanning line, and the second scanning line number is substantially equal to the first scanning line number. As described above, the thinning window generating means for outputting the signal for invalidating the pulse of the 1H cycle, the vertical scanning means for scanning the gate lines, and the horizontal scanning means for scanning the signal lines are driven at a predetermined timing. Pulse generating means for generating a drive pulse based on the pulse from the internal timing pulse generating means, and in the case of the second mode, the drive pulse generated by the pulse generating means is the thinning window. By the action of the generating means, the non-inversion state or the thinning is performed once in the predetermined number of times.

In the flat panel display device and its driving circuit, it is preferable that the thinning window generating means has a Johnson counter and a 2-bit decoder. Further, it is preferable that the thinning-out window generating means makes the timing of once every predetermined number of times, the thinning-out address is different between the odd field and the even field.

The flat display device of the present invention is, for example, a liquid crystal display device.

[0012]

In the flat display device and the driving method thereof according to the present invention, in the case of the first mode, a normal drive pulse for displaying the image signal of the first mode on the front surface of the screen is generated, for example, the screen of the liquid crystal display device. The image of the first mode is displayed on the entire surface.

In the case of the second mode, the thinning window generating means acts so that the second scanning line number becomes substantially equal to the first scanning line number once in a predetermined number of times. Then, a signal for invalidating the pulse of the 1H cycle is output. By combining the invalidating signal and the pulse from the internal timing pulse generating means through the logic circuit, it is possible to generate the thinned drive signal. If the flat panel display device is driven by using this drive signal, the second mode having a larger number of scanning lines than the first mode is used.
The mode video signal can be displayed on the flat display device for the first mode.

According to the present invention in which the thinning-out window generating means is composed of a logic circuit having a Johnson counter and a 2-bit decoder, the circuit structure is remarkably simplified, the reliability of the circuit is improved, and the manufacturing cost is reduced. It also contributes to reduction.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A flat panel display device and its drive circuit according to an embodiment of the present invention will be described in detail below with reference to the drawings. 1 is an equivalent circuit diagram of a main part of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a block diagram of a drive signal generation device of the liquid crystal display device according to the embodiment, and FIG. 3 is a drive signal shown in FIG. A specific logic circuit diagram showing the main part of the generator, FIG.
Is a concrete logic circuit diagram of the thinning window generating means shown in FIG. 2, FIG. 5 is a pulse waveform diagram showing an example of a drive signal, FIG. 6 is a timing chart diagram showing an example of a drive signal, and FIGS. Timing chart showing an example of
9 is a logic circuit diagram for normalizing the thinned drive pulse waveform, FIG. 10 is a diagram showing a positive loop output state by a Johnson counter of the thinning window generating means shown in FIG. 4, and FIG. 11 is a liquid crystal display device. It is the schematic which shows the change state of the polarity of the applied voltage.

In the embodiments described below, the present invention is applied to a liquid crystal display device. However, the present invention is not limited to the liquid crystal display device, but the present invention is applied to a flat display using an active matrix substrate or the like. The same applies to all devices. In the following description, the first mode is the NTSC system with 525 scanning lines, and the second mode is
Although the mode will be described as a PAL system having 625 scanning lines, other than these systems, there are SECAM systems and the like, and the specific number of scanning lines and the video system are not particularly limited in the present invention.

First, the liquid crystal display device 10 shown in FIG. 1 will be described. The liquid crystal display device 10 generally has an active matrix substrate on which a number of gate lines G1, G2 ... Gn corresponding to the number of the first scanning lines are arranged so as to be substantially orthogonal to the gate lines. The arranged signal lines S1 and S
2 ... Sn are formed. Gate lines G1, G2 ... Gn
N corresponds to the NTSC system, which is the first mode,
Since the number of scanning lines in the TSC system is 625 and one image is displayed in two fields, the number of scanning lines is 262.5 or more, which is half of 625. The gate lines G1 and G2
.. Gn and the signal lines S1, S2 ... Sn may be substantially orthogonal to each other as a whole, and microscopically, the signal lines S1, S2
2 ... Sn or the gate lines G1, G2 ... Gn may meander. For example, in the delta arrangement, the signal line S
1, S2 ... Sn meanders.

The gate lines G1, G2 ... Gn and the signal lines S1,
An intersection with S2 ... Sn corresponds to one pixel, and a switch element 12 formed of, for example, a TFT is provided at this intersection.
And the capacitive element 8 are built in. A counter substrate on which a common electrode is formed via a liquid crystal layer is arranged on the active matrix substrate. As a result, as shown in FIG. 1, the liquid crystal 6 for each pixel is connected in parallel to the capacitive element 8.
By selectively applying a voltage to the liquid crystal 6 for each pixel, the molecular arrangement of the liquid crystal part is partially changed for each pixel, and an image can be displayed.

A vertical shift register 2 as a vertical scanning means is connected to the gate lines G1, G2 ... Gn so that the gate lines G1, G2 ... Gn can be sequentially scanned. Further, the signal lines S1, S2 ... Sn are connected to the video input lines 14R, 14G, 14 via the scanning switch 16.
It is connected to B. Video input lines 14R, 14G, 14B
The video signal is input from the signal lines to the signal lines S1, S2 ... Sn. In this embodiment, three types of input lines for R, G, and B are used as the video input lines, but a single-line input line can be used when a color image is not required.

The scanning switch 16 is, through an output logic circuit, a horizontal scanning shift register 4 as horizontal scanning means.
The scanning switch 16 is sequentially opened in response to the scanning signal from the horizontal shift register 4, and the gate line G
1, G2 ... Gn in synchronism with the scanning of the video signal on the signal line S
Send to 1, S2 ... Sn.

In order to drive such a liquid crystal display device 10, drive signals (HST, HCK1,
HCK2, VST, VCK1, VCK2) must be input. In this embodiment, these drive signals (HST, H
CK1, HCK2, VST, VCK1, VCK2)
It is generated by the drive signal generation device shown in FIG. This drive signal generator has a horizontal sync signal detecting means 20 and a vertical sync signal detecting means 22 for detecting a horizontal sync signal and a vertical sync signal of the composite sync signal. The horizontal synchronizing signal detecting means 20 is an internal timing generating means 24.
Connected to. Internal timing pulse generation means 24
Is composed of, for example, a 638-ary counter and generates a reference pulse AFH having a period of 1H.
Pulse HST-TRG1, decoded for FH
Generate HST-TRG2. Waveforms of these pulses in the first mode (NTSC method) are shown in FIG.
Shown in (4) and (5).

The reference pulse AFH generated by the internal timing generating means 24 is supplied to the VD generating means 28 and VD-OUT.
It is adapted to be transmitted to the generation means 26, the VCK generation means 36 of the drive pulse generation means 32, and the FRP generation means 38 of the drive pulse generation means 32. In addition, the HST-TRG generated by the internal timing pulse generation means 24
1, HST-TRG2 pulses are drive pulse generating means 3
2 is transmitted to the HST generating means.

The VD generating means 28 receives the signal from the vertical synchronizing signal detecting means 22 and the AFH pulse signal, and generates a VD pulse signal based on this. The VD pulse signal is a reset signal for changing the polarity of voltage application for each field, and its waveform is shown in FIG. 7 (2).

The VD-OUT generating means 26 generates a VD-OUT signal based on the AFH pulse signal and the VD pulse signal. The VD-OUT signal is used to reset the counter used in the thinning window generating means 30, and is sent to the drive pulse generating means 32 and the thinning window generating means 30. The waveform of the VD-OUT signal is shown in FIG. 7 (3).

The thinning-out window generating means 30 has a scanning line number 31 for one field in the PAL system which is the second mode.
A reference pulse signal of 1H period is generated at a timing of once every 7 times so that 2.5 to 5 lines are substantially equal to the number of scanning lines of 262.5 lines for one field of the NTSC system which is the first mode. Signal to disable AFH (XMA2EV, XM
A5OD, XMA3EV, XMA6OD) is output.
An example of the signal is shown in FIG. FIG. 8 (0) exemplifies a signal XMA3EV that invalidates the AFH pulse signal of the third address of the seven times. Details of the thinning window generating means 30 are shown in FIG. 4 and will be described later.

The drive pulse generating means 32 is an HST generating means 34, a VCK generating means 36, and an FRP generating means 38.
And EN generating means 40. HST generation means 36
Generates a start signal for starting the horizontal shift register 4 shown in FIG. The waveform of the signal is NTSC
In the system mode, for example, as shown in FIG.
In the mode, the display is (6) in FIG. In FIG. 8, the dotted line pulse indicates thinning.

The VCK generating means 36 is a drive pulse signal VCK for driving the vertical shift register 2 shown in FIG.
1 and VCK2 are generated. The drive pulse signal VCK
Waveforms of 1 and VCK2 are shown in FIGS. FIG. 5A shows a drive pulse signal in the case of the NTSC mode, and the low level and the high level are repeated every 1H. FIG. 5B shows the drive pulse signal in the case of the PAL system mode, which is in the non-inverted state once every 7H, and the low level or the high level continues for the time of 2H.

It should be noted that VCK1 and VCK2 are complementary signals and are similar signals except that the high level and the low level are in the opposite relationship, and in the following description, VCK1
Will be described as a representative. The reason why VCK2 is used in addition to VCK1 is to improve the driving reliability. Also,
The VST shown in FIG. 5 is the vertical shift register 2 shown in FIG.
Is a signal for starting every 1 field,
It becomes high level in one field cycle. The means for generating this signal is omitted in the diagram shown in FIG.
It can be generated in the same manner as D-OUT. Also,
In addition to the HST signal, HCK1 and HCK2 are also input to the horizontal shift register 4 shown in FIG. 1, and the horizontal register 4 is driven based on this, but means for generating HCK1 and HCK2 is omitted in FIG. There is. HCK
1, HCK2, the signal lines S1, S2 ... Sn during 1H
Has a signal waveform for driving the horizontal shift register 4 so as to sequentially scan.

The FRP generating means 38 of FIG. 2 generates a signal FRP for inverting the electric field acting on the liquid crystal 6 for each field and for each of the gate lines G1, G2 ... Gn.
This FRP has a waveform similar to VCK1 or VCK2. 11A and 11B are schematic diagrams in which the electric field is inverted for each field. The reason for reversing the electric field is to protect the liquid crystal. This is because if an electric field in the same direction is always applied to the liquid crystal, the liquid crystal may be degraded due to electrolysis or the like, and this is prevented.

Further, the EN generation means 40 of FIG.
Transformed VCK at a rate of once every 7H in system mode
This is a circuit for masking the first half in accordance with the pulse of 1 or VCK2. The operation of this EN pulse signal is shown in FIG. 9, the details of which will be described later.

The switching signal from the mode switching means 42 is input to the drive pulse generating means 32, and the NTSC
The mode state can be switched between the system and the PAL system. In the NTSC system, the output signal from the thinning window generating means 30 is unnecessary. Therefore, the drive pulse generating means 32 is responsive to the signal from the mode switching means 42 to generate the thinning window generating means 3.
There is a built-in logic circuit that invalidates or ignores the output signal from 0.

Next, the details of the drive pulse generating means 32 will be described.
It will be described with reference to FIG. In the logic circuit shown in FIG. 3, VD
The -OUT generation means 26 is also incorporated. First, VD
The -OUT generation means 26 will be described. In the embodiment shown in FIG. 3, the VD-OUT generating means 26 has an input terminal 52.
, Input terminal 54, inverter gate 68, AND
A gate 69, an OR gate 70, a D-type flip-flop 82, and a D-type flip-flop 84 with an enable terminal.
And an output terminal 90. By using these logic circuits, the VD-OUT signal shown in FIGS. 7 and 8 is output from the output terminal 90 from the signal VD and the signal AFH input from the input terminals 52 and 54, respectively. The H-TIM2 input to the enable terminal EN of the D-type flip-flop 84 with an enable terminal is a signal for timing adjustment. A clock signal is input to the terminals CK of the flip-flops 82 and 84.

HS in the drive pulse generating means in FIG.
The T generation means 34 has input terminals 50, 5 in FIG.
1, 57, 58, 59, a selector 63, a NAND gate 71, an AND gate 72, and a NOR gate 73.
And a D-type flip-flop 83 and an output terminal 91. From the input terminals 50, 51, 57, 58, 59, respectively, HST-TRG1, HST-TRG2, X
By inputting signals MA3EV, XMA6OD, FIELD, an HST pulse signal as shown in FIG. 8 (6) is output. That is, the HST pulse signal is basically HST-T based on the logic of the JK flip-flop.
It is started at the timing of RG1 and the next HST-TR
It is generated so as to be dropped at the timing of G2.
The HST pulse signal shown in FIG. 8 (6) is in the PAL mode, and pulses are thinned out once every seven times as shown by the dotted line in FIG. 8 (6).

HST is a signal for driving the horizontal shift register 4 shown in FIG. 1. In this HST,
The position of the pulse to be decimated needs to correspond to the position of VCK1 to be decimated. VCK1 is a signal for driving the vertical shift register 2 shown in FIG. 1, and sequentially scans the gate lines G1, G2 ... Gn. In the present embodiment, as will be described later, in the sequential scanning of the gate lines G1, G2 ... Gn, the scanning is stopped once for 7H for 1H time. Therefore, during the scanning stop, Signal lines S1 and S
2 It is necessary to prevent the video signal from being sent to Sn. Therefore, in this embodiment, in synchronization with VCK1,
The HST pulse is thinned out once every 7 pulses.

In the circuit shown in FIG. 3, the selector for mode switching is omitted. In the actual device,
The mode is switched according to the signal from the mode switching signal means 42 shown in FIG. That is,
In the NTSC mode, the output signal from the select 63 or the thinning window generating means 30 shown in FIG.
7 (6) at the output terminal 91, which is invalid or ignored.
As shown in, the HST signal that is not thinned out is output.
The input terminals 57 and 58 to the selector 63 are the output terminals 116 of the logic circuit for the thinning window generating means shown in FIG.
It is connected to 124. The description of FIG. 4 will be given later. The FIELD signal is input to the input terminal 59 of the selector 63,
In the even field and the odd field, the input terminals 57,
58 selections are made. That is, in the even field,
Select the input terminal 57 and output XMA3EV to the terminal X
In the odd field, the input terminal 58 is selected and its output XMA6OD is output from the terminal X.

The VCK generating means 36 in the drive pulse generating means 32 in FIG.
53, 54, 55, 56, 59, selector 62, A
An ND gate 66, an OR gate 67, an exclusive OR gate 78, an inverter 79, an AND gate 80, a D-type flip-flop 81, D-type flip-flops 86 and 87 with an enable terminal, and an output terminal 9
3, 94. In this embodiment, the D-type flip-flop 81 is connected so as to form a T-type flip-flop.

Input terminals 52, 53, 54, 55, 56,
59, VD, VD-OUT, AFH, XM respectively
By inputting signals of A2EV, XMA5OD, FIELD, VCK1 (VCK2 as shown in FIG.
Outputs a pulse signal having a complementary relationship with VCK1 as shown in FIG. This VCK1 pulse signal is in the case of the PAL mode, and once every 7H, as shown in FIG. 8 (7), maintains the non-inverted state for 2H. In addition, in the NTSC mode, FIG.
As shown in (7), VCK1 is inverted every 1H and repeats high level and low level. In the example shown in FIG. 3, N
Although the means for switching between the TSC system mode and the PAL system mode is omitted, in an actual device, it is necessary to switch by a selector or the like. That is, in the NTSC mode, it is necessary to invalidate or ignore the output from the selector 62 or the window generating means 30 shown in FIG. By ignoring or disabling these outputs,
From the output terminal 93, as shown in FIG. 7 (7), a normal drive signal in which the inversion of the high level and the low level is repeated in the 1H cycle is obtained.

Drive signal V in the NTSC mode
CK1, the output of the vertical shift register 2, and the gate line G
The relationship with the voltage acting on 1, G2 ... Gn is shown in FIG. In addition, the drive signal VC in the PAL system mode
K1, the output of the vertical shift register 2 and the gate line G1
, G2 ... Gn is shown in FIG. 6 (B). In the PAL mode, the operation of the thinning window generating means 30 shown in FIG.
Once every 2 hours, the non-inversion state is set, and during that time, the voltage is applied to the specific gate line (G1 in FIG. 6B) for 2H time. As a result, in the PAL mode, the vertical scanning can be stopped by turning on the switch element located on the gate line scheduled to turn on 1H before again.

However, with this, 1H which is originally unnecessary
During the period, the switch element 12 is turned on,
Leakage to pixels may occur. Therefore, in the present embodiment, in order to prevent the leak to the pixel and synchronize the switch element 12, as shown in FIG. 9, the first half 1H period i in the non-inverted state signal G1 in which the vertical scanning is stopped is performed.
In order to eliminate the above, the active EN signal is input to one input terminal 156 of the NAND gate 150 and G1 is input from the other input terminal 154 through the inverter 152. The EN signal is the EN generating means 40 shown in FIG.
Is generated by. The logic circuits 150 and 152 can be provided, for example, in the vertical shift register 2 shown in FIG. 1, but can also be provided in the drive pulse generating means 32 shown in FIG. In the specific circuit shown in FIG. 3, the logic circuits 150 and 152 are omitted.

The FRP generating means 38 in the drive pulse generating means 32 in FIG.
53, 54, 55, 56, 59, selector 62, A
It comprises an ND gate 64, an OR gate 65, an exclusive OR gate 74, an inverter 75, an AND gate 76, a D-type flip-flop 77, a D-type flip-flop 85 with an enable terminal, and an output terminal 92. There is. In this embodiment, the D-type flip-flop 77
Are connected to form a T-type flip-flop.

The logic circuit forming the FRP generating means is similar to the logic circuit forming the VCK generating means 36 described above and has an output waveform similar to that of VCK1. The FRP signal obtained from the output terminal 92 is, as described above,
For each field and for each gate line G1, G2 ... Gn,
This is a signal for reversing the electric field acting on the liquid crystal 6.
A schematic diagram of the state where the electric field is reversed for each field,
This is shown in FIGS. 11 (A) and 11 (B). This FRP signal is also PA
In the L mode, like the VCK1 signal, the non-inversion state needs to be set once every 7H. By doing so, the polarity of the voltage is prevented from being the same for the liquid crystal pixels in the portions corresponding to the adjacent gate lines. That is, even in the PAL mode, as shown in FIGS. 11 (A) and 11 (B), the polarity is alternately inverted for each line.

The EN generating means 40 in the drive pulse generating means 32 in FIG. 2 has the input terminals 57, 5 in FIG.
8, 59, a selector 63, a D-type flip-flop 88 with an enable terminal, and an output terminal 95. The EN signal output from the output terminal 95 is either the XMA3EV or XMA6OD signal selected by the selector 63, and has the waveform shown in FIG. 8 (0) or FIG. 9, for example. EN output from the output terminal 95
As shown in FIG. 9, the signal is the first half portion i of the output signal G1 in the non-inverted state corresponding to the portion where the vertical scanning is thinned out.
This is a signal for excluding (1H period).

In FIG. 3, flip-flops 85 and 8 are provided.
The HTIM1 signal for timing adjustment is input to the EN terminals of 6, 87, and 88. Next, a specific logic circuit of the thinning window generating means 30 shown in FIG. 2 will be described with reference to FIG.

As shown in FIG. 4, the thinning window generating means 30 of this embodiment has input terminals 96, 97, 98 and 9.
9 and output terminals 112, 116, 120 and 124. The VD-OUT signal from the output terminal 90 shown in FIG. 3 is input from the input terminal 96. The AFH signal generated by the internal timing generating means 24 shown in FIG. 2 is input from the input terminal 97. The clock signal CLOCK is input from the input terminal 98. The reset signal CLEAR is input from the input terminal 99.

In this embodiment, the invert AND gate 1
00, 102, 104, 107 and D-type flip-flops with enable terminals 101, 103, 106, 108
And the NAND gate 105 are connected as shown in the figure to form a 1/7 Johnson counter. In this Johnson counter, the AFH from the input terminal 97
Based on the signal, it counts up every 1H. The positive loop of this Johnson counter is shown in FIG. Figure 1
0, the counter values MA0, MA1, MA2, MA3 are
The flip-flops 101, 103, 106 shown in FIG.
It is an output signal obtained from each Q terminal of 108.

Each flip-flop 101, 103, 10
6,108 outputs MA0, XMA0, MA1, XMA
Of the 1, MA2, XMA2, and MA3, the MA0 signal is input to the input terminal 117 of the decoder, the XMA0 signal is input to the input terminal 109, the MA1 signal is input to the input terminals 110 and 121, and the XMA1 signal is , MA2 signal is input to the input terminal 114, and XMA2 is input to the input terminal 122. The decoder has four NAND gates 111,
115, 119, and 123, and the addresses 2, 3, 5, and 6 shown in FIG. 10 are decoded by 2 bits (see FIG.
Circled bits in 0), output terminals 112, 11
6, 120, and 124 are corresponding addresses and have low active pulses XMA2EV, XMA3EV, 1H wide,
XMA5OD and XMA6OD are obtained.

The output terminal 112 is the input terminal 5 shown in FIG.
5, the output terminal 116 is connected to the input terminal 57, the output terminal 120 is connected to the input terminal 56, and the output terminal 124 is connected to the input terminal 58. For example, an example of the output signal XMA3EV for the thinning window input from the output terminal 116 to the input terminal 57 is shown in FIG.
Shown in. At address 3 in the even field, the low active pulse has a width of 1H. When this pulse is input to the AND gate 64 shown in FIG. 3 and is multiplied by the AFH pulse signal, 3 out of 7 times is generated in the even field.
No. address, the AFH pulse becomes invalid, and the output terminal 92 obtains a corresponding FRP output signal. In the odd field, the selector 62
The signal from the input terminal 56 is selected, and the AFH signal becomes invalid at the fifth address out of seven times. Similarly, in the selector 63, even field and odd field,
The input signals from the input terminals 57 and 58 are selected, the AFH signal is invalidated at the third address in the even field and the sixth address in the odd field, and the output drive signal VCK1 is non-inverted at the portion corresponding to the address. It becomes a state. Further, the output drive signal HST is thinned correspondingly.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, in the above embodiment, the even numbered fields and the odd numbered fields are changed in the number of thinned out addresses of 7 times to 2, 3, 5 and 6, but other addresses may be used. It may be the same address. However, the FRP signal is the other drive signal VCK.
It is preferable that the thinning window processing is performed on the immediately preceding address for 1, VCK2 and HST.

Further, according to the number of scanning lines, the AFH invalidating pulse signal is thinned out not once in seven times but once in a plurality of times or at a rate of several times in a plurality of times. It can also be generated from the window generating means 30.

[0050]

As described above, according to the present invention, in a flat panel display device such as a liquid crystal display device, NT
Even when a video signal having a different number of scanning lines is input as in the SC system, the PAL system, or the SECAM, a part of one of the images is not disabled,
Both can be displayed well. Further, the circuit structure for that purpose is remarkably simplified, the reliability of the circuit is improved, and the manufacturing cost is reduced.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a drive signal generator of the liquid crystal display device according to the embodiment.

FIG. 3 is a specific logic circuit diagram showing a main part of the drive signal generator shown in FIG.

FIG. 4 is a specific logic circuit diagram of the thinning window generating means shown in FIG.

FIG. 5 is a pulse waveform diagram showing an example of a drive signal.

FIG. 6 is a timing chart showing an example of a drive signal.

FIG. 7 is a timing chart in the NTSC system mode showing an example of a drive signal.

FIG. 8 is a timing chart in the PAL system mode showing an example of a drive signal.

FIG. 9 is a logic circuit diagram for normalizing a thinned drive pulse waveform.

10 is a diagram showing a positive loop output state by a Johnson counter of the thinning window generating means shown in FIG.

FIG. 11 is a schematic diagram showing a change state of the polarity of the voltage applied to the liquid crystal display device.

[Explanation of symbols]

 2 ... Vertical shift register 4 ... Horizontal shift register 6 ... Liquid crystal 8 ... Capacitance element 10 ... Liquid crystal display device 12 ... Switch elements 14R, 14G, 14B ... Image input lines S1, S2 ... Sn ... Signal lines G1, G2 ... Gn ... Gate Line 20 ... Horizontal sync detection means 22 ... Vertical sync signal detection means 24 ... Internal timing pulse generation means 26 ... VD-OUT generation means 28 ... VD generation means 30 ... Thinning window generation means 32 ... Drive pulse generation means 34 ... HST generation means 36 ... VCK generation means 38 ... FRP generation means 40 ... EN generation means 42 ... Mode switching means HST, VCK1, VCK2, FRP ... Drive signal

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[Procedure amendment]

[Submission date] January 28, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Specifically, the flat panel display device of the present invention corresponds to the first number of scanning lines in synchronization with the number of gate lines corresponding to the first number of scanning lines and the scanning of the gate lines. A flat display device comprising at least a signal line to which a video signal is input and arranged so as to be substantially orthogonal to a gate line, and a pixel formed at an intersection of the gate line and the signal line. A second mode in which a video signal corresponding to a second number of scanning lines greater than one scanning line is input, and a first mode in which a video signal corresponding to the first number of scanning lines is input. Mode switching means for switching the mode state, internal timing pulse generating means for generating a pulse of 1H period corresponding to the first scanning line, and the second scanning line number is substantially equal to the first scanning line number. 1 at a given time so that
The pulse for driving the thinning window generating means for outputting the signal for invalidating the pulse of the 1H cycle, the vertical scanning means for scanning the gate line and the horizontal scanning means for scanning the signal line at the timing of Pulse generation means for generating based on the pulse from the internal timing pulse generation means, and in the case of the second mode, the drive pulse generated by the pulse generation means, by the action of the thinning window generation means, It is characterized in that the non-inversion state or the thinning is performed once in the predetermined number of times.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

Further, in the driving device of the planar driving device of the present invention, the second mode in which the video signal corresponding to the second scanning line number larger than the first scanning line number is input, and the first scanning With the first mode in which the video signal corresponding to the number of lines is input,
Mode switching means for switching the mode state, internal timing pulse generating means for generating a pulse of 1H period corresponding to the first scanning line, and the second scanning line number is substantially equal to the first scanning line number. As described above, the thinning window generating means for outputting the signal for invalidating the pulse of the 1H cycle, the vertical scanning means for scanning the gate lines, and the horizontal scanning means for scanning the signal lines are driven at a predetermined timing. Pulse generating means for generating a drive pulse based on the pulse from the internal timing pulse generating means, and in the case of the second mode, the drive pulse generated by the pulse generating means is the thinning window. By the action of the generating means, the non-inversion state or the thinning is performed once in the predetermined number of times.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

First, the liquid crystal display device 10 shown in FIG. 1 will be described. The liquid crystal display device 10 generally has an active matrix substrate on which a number of gate lines G1, G2 ... Gn corresponding to the number of the first scanning lines are arranged so as to be substantially orthogonal to the gate lines. The arranged signal lines S1 and S
2 ... Sn are formed. Gate lines G1, G2 ... Gn
N corresponds to the NTSC system, which is the first mode,
Since the number of scanning lines in the TSC system is 525 and one image is displayed in two fields, it is 262.5 or more, which is half of 525 . The gate lines G1 and G2
.. Gn and the signal lines S1, S2 ... Sn may be substantially orthogonal to each other as a whole, and microscopically, the signal lines S1, S2
2 ... Sn or the gate lines G1, G2 ... Gn may meander. For example, in the delta arrangement, the signal line S
1, S2 ... Sn meanders.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

A vertical shift register 2 as a vertical scanning means is connected to the gate lines G1, G2 ... Gn so that the gate lines G1, G2 ... Gn can be sequentially scanned. Further, the signal lines S1, S2 ... Sn are connected to the video input lines 14R, 14 via the signal line scanning switch 16.
It is connected to G and 14B. Video input lines 14R, 14
Video signals are input from G and 14B to the signal lines S1, S2 ... Sn. In this embodiment, three types of input lines for R, G, and B are used as the video input lines, but a single-line input line can be used when a color image is not required.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

The signal line scanning switch 16 through the output logic circuits, Yes and connected to a horizontal scanning shift register 4 serving as a horizontal scanning unit, in accordance with the scanning signals from the horizontal shift register 4, signal line scanning switch 16 Sequentially open, and the video signals are transmitted to the signal lines S1, S2 ... Sn in synchronization with the scanning of the gate lines G1, G2 ... Gn.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

Next, the details of the drive pulse generating means 32 will be described.
It will be described with reference to FIG. In the logic circuit shown in FIG. 3, VD
The -OUT generation means 26 is also incorporated. First, VD
The -OUT generation means 26 will be described. In the embodiment shown in FIG. 3, the VD-OUT generating means 26 has an input terminal 52.
, Input terminal 54, inverter gate 68, AND
Gate 69, an OR gate 70, a D-type flip-flop 82, enable D-type with terminal flip-flop 84
And an output terminal 90. By using these logic circuits, the VD-OUT signal shown in FIGS. 7 and 8 is output from the output terminal 90 from the signal VD and the signal AFH input from the input terminals 52 and 54, respectively. Incidentally, H-TIM2 is input to enable terminal EN of the Lee Ne <br/> Buru terminal with the D-type flip-flop 84 is a signal for timing adjustment. Also, flip-flop 8
A clock signal is input to the terminals CK of 2, 84.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The VCK generating means 36 in the drive pulse generating means 32 in FIG.
53, 54, 55, 56, 59, selector 62, A
And ND gate 66, an OR gate 67, an exclusive OR gate 78, an inverter 79, an AND gate 80, a D-type flip-flop 81, the D-type flip-flop 86 and 87 with enable terminal, an output terminal 93,
And 94. In this embodiment, the D-type flip-flop 81 is connected so as to form a T-type flip-flop.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

However, with this, 1H which is originally unnecessary
During the period, the switch element 12 is turned on,
Leakage to pixels may occur. Therefore, in the present embodiment, in order to prevent the leak to the pixel and synchronize the switch element 12, as shown in FIG. 9, the first half 1H period i in the non-inverted state signal G1 in which the vertical scanning is stopped is performed.
NAND the low active EN signal to eliminate
One of the input terminals 156 of the gate 150 is input, and the other input terminal 154 is input with G1 through the inverter 152. The EN signal is generated by the EN generation means 40 shown in FIG. The logic circuits 150 and 152 can be provided, for example, in the vertical shift register 2 shown in FIG. 1, but can also be provided in the drive pulse generating means 32 shown in FIG. In the specific circuit shown in FIG. 3, the logic circuits 150 and 152 are omitted.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

The EN generating means 40 in the drive pulse generating means 32 in FIG. 2 has the input terminals 57, 5 in FIG.
And 8,59, a selector 63, an enable D-type flip-flop 88 with the terminal, are constituted by the output terminal 95. The EN signal output from the output terminal 95 is either the XMA3EV or XMA6OD signal selected by the selector 63, and has the waveform shown in FIG. 8 (0) or FIG. 9, for example. EN output from the output terminal 95
As shown in FIG. 9, the signal is the first half portion i of the output signal G1 in the non-inverted state corresponding to the portion where the vertical scanning is thinned out.
This is a signal for excluding (1H period).

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

In FIG. 3, flip-flops 85 and 8 are provided.
The H - TIM1 signal for timing adjustment is input to the EN terminals of 6, 87, and 88. Next, a specific logic circuit of the thinning window generating means 30 shown in FIG. 2 will be described with reference to FIG.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

In this embodiment, the invert AND gate 1
And 00,102,104,107, D with enable terminal
Type flip-flops 101, 103, 106, 108
And the NAND gate 105 are connected as shown in the figure to form a 1/7 Johnson counter. In this Johnson counter, the AFH from the input terminal 97
Based on the signal, it counts up every 1H. The positive loop of this Johnson counter is shown in FIG. Figure 1
0, the counter values MA0, MA1, MA2, MA3 are
The flip-flops 101, 103, 106 shown in FIG.
It is an output signal obtained from each Q terminal of 108.

Claims (8)

[Claims] 1. A number of gate lines corresponding to the first number of scanning lines and a video signal corresponding to the first number of scanning lines are input in synchronization with the scanning of the gate lines, and the gate lines are substantially connected. A flat display device having at least a signal line arranged so as to be orthogonal to the pixel line and a pixel formed at an intersection of the gate line and the signal line; A first mode in which a video signal corresponding to the number of scanning lines is input, and a second mode in which a video signal corresponding to the first number of scanning lines is input
Mode switching means for switching the mode state, internal timing pulse generating means for generating a pulse of 1H period corresponding to the first scanning line, and second scanning line number is substantially equal to the first scanning line number. As described above, a thinning window generating means for outputting a signal for invalidating the pulse of the 1H cycle at a predetermined timing, a vertical scanning means for scanning the gate line, and a horizontal scanning for scanning the signal line. Pulse generating means for generating a pulse for driving the means based on the pulse from the internal timing pulse generating means, and in the case of the second mode, the drive pulse generated by the pulse generating means is A flat display device which is non-inverted or decimated once every predetermined number of times by the action of the decimating window generating means. 2. The flat panel display device according to claim 1, wherein the thinning window generating means includes a Johnson counter and a 2-bit decoder. 3. The flat panel display device according to claim 1, wherein the thinning-out window generating means has a timing of once in a predetermined number of times, wherein the thinning-out addresses are different between the odd field and the even field. 4. The flat display device according to claim 1, wherein the flat display device is a liquid crystal display device. 5. A number of gate lines corresponding to the first number of scanning lines and a video signal corresponding to the first number of scanning lines are input in synchronization with the scanning of the gate lines, and the gate lines are substantially connected. Is a drive circuit for driving a flat display device having at least a signal line arranged so as to be orthogonal to each other and a pixel formed at an intersection of the gate line and the signal line, wherein the first scanning line A first mode in which a video signal corresponding to a larger number of second scanning lines is input, and a second mode in which a video signal corresponding to the first number of scanning lines is input.
Mode switching means for switching the mode state, internal timing pulse generating means for generating a pulse of 1H period corresponding to the first scanning line, and second scanning line number is substantially equal to the first scanning line number. As described above, a thinning window generating means for outputting a signal for invalidating the pulse of the 1H cycle at a predetermined timing, a vertical scanning means for scanning the gate line, and a horizontal scanning for scanning the signal line. Pulse generating means for generating a drive pulse for driving the means based on the pulse from the internal timing pulse generating means, and in the case of the second mode, the drive pulse generated by the pulse generating means, A drive circuit for a flat display device, which is non-inverted or decimated once every predetermined number of times by the action of the decimating window generating means. 6. The drive circuit for a flat panel display device according to claim 5, wherein the thinning window generating means includes a Johnson counter and a 2-bit decoder. 7. The plane according to claim 5, wherein the thinning window generating means sets the timing once every predetermined number of times so that the thinning addresses are different between the odd field and the even field. Drive circuit of display device. 8. The drive circuit for a flat display device according to claim 5, wherein the flat display device is a liquid crystal display device.