AU2016284002A1 - Coherency driven enhancements to a peripheral component interconnect (PCI) express (PCIe) transaction layer - Google Patents

Coherency driven enhancements to a peripheral component interconnect (PCI) express (PCIe) transaction layer Download PDF

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Publication number
AU2016284002A1
AU2016284002A1 AU2016284002A AU2016284002A AU2016284002A1 AU 2016284002 A1 AU2016284002 A1 AU 2016284002A1 AU 2016284002 A AU2016284002 A AU 2016284002A AU 2016284002 A AU2016284002 A AU 2016284002A AU 2016284002 A1 AU2016284002 A1 AU 2016284002A1
Authority
AU
Australia
Prior art keywords
address range
endpoint
ownership
data associated
pcie
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2016284002A
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English (en)
Inventor
Amit Gil
James Lionel Panian
Ofer Rosenberg
Shaul Yohai Yifrach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of AU2016284002A1 publication Critical patent/AU2016284002A1/en
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
AU2016284002A 2015-06-22 2016-06-17 Coherency driven enhancements to a peripheral component interconnect (PCI) express (PCIe) transaction layer Abandoned AU2016284002A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562182815P 2015-06-22 2015-06-22
US62/182,815 2015-06-22
US15/184,181 US20160371222A1 (en) 2015-06-22 2016-06-16 COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER
US15/184,181 2016-06-16
PCT/US2016/038146 WO2016209733A1 (en) 2015-06-22 2016-06-17 Coherency driven enhancements to a peripheral component interconnect (pci) express (pcie) transaction layer

Publications (1)

Publication Number Publication Date
AU2016284002A1 true AU2016284002A1 (en) 2017-11-23

Family

ID=56297124

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2016284002A Abandoned AU2016284002A1 (en) 2015-06-22 2016-06-17 Coherency driven enhancements to a peripheral component interconnect (PCI) express (PCIe) transaction layer

Country Status (9)

Country Link
US (1) US20160371222A1 (enExample)
EP (1) EP3311279A1 (enExample)
JP (1) JP2018518777A (enExample)
KR (1) KR20180019595A (enExample)
CN (1) CN107980127A (enExample)
AU (1) AU2016284002A1 (enExample)
BR (1) BR112017027806A2 (enExample)
TW (1) TW201701165A (enExample)
WO (1) WO2016209733A1 (enExample)

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Publication number Priority date Publication date Assignee Title
US10484015B2 (en) 2016-12-28 2019-11-19 Amazon Technologies, Inc. Data storage system with enforced fencing
US10514847B2 (en) 2016-12-28 2019-12-24 Amazon Technologies, Inc. Data storage system with multiple durability levels
US10771550B2 (en) 2016-12-28 2020-09-08 Amazon Technologies, Inc. Data storage system with redundant internal networks
US11301144B2 (en) * 2016-12-28 2022-04-12 Amazon Technologies, Inc. Data storage system
US10474620B2 (en) 2017-01-03 2019-11-12 Dell Products, L.P. System and method for improving peripheral component interface express bus performance in an information handling system
US11010064B2 (en) 2017-02-15 2021-05-18 Amazon Technologies, Inc. Data system with flush views
WO2018186454A1 (ja) * 2017-04-07 2018-10-11 パナソニックＩｐマネジメント株式会社 情報処理装置
US10366027B2 (en) * 2017-11-29 2019-07-30 Advanced Micro Devices, Inc. I/O writes with cache steering
US11169723B2 (en) 2019-06-28 2021-11-09 Amazon Technologies, Inc. Data storage system with metadata check-pointing
US12423437B2 (en) * 2021-09-23 2025-09-23 International Business Machines Corporation Fuzzing based security assessment

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JP2675981B2 (ja) * 1993-09-20 1997-11-12 インターナショナル・ビジネス・マシーンズ・コーポレイション スヌープ・プッシュ・オペレーションを回避する方法
US6018792A (en) * 1997-07-02 2000-01-25 Micron Electronics, Inc. Apparatus for performing a low latency memory read with concurrent snoop
US20040128269A1 (en) * 2002-12-27 2004-07-01 Milligan Charles A. System and method for managing data through families of inter-related metadata tables
US7162706B2 (en) * 2004-03-05 2007-01-09 Picocraft Design Systems, Inc. Method for analyzing and validating clock integration properties in circuit systems
US20070233928A1 (en) * 2006-03-31 2007-10-04 Robert Gough Mechanism and apparatus for dynamically providing required resources for a hot-added PCI express endpoint or hierarchy
US7860930B2 (en) * 2006-12-19 2010-12-28 International Business Machines Corporation Communication between host systems using a transaction protocol and shared memories
US7836129B2 (en) * 2006-12-19 2010-11-16 International Business Machines Corporation Communication between host systems using a queuing system and shared memories
US20090006668A1 (en) * 2007-06-28 2009-01-01 Anil Vasudevan Performing direct data transactions with a cache memory
CN101178697B (zh) * 2007-12-12 2011-08-03 杭州华三通信技术有限公司 一种pcie设备通信方法及系统
CN101276318B (zh) * 2008-05-12 2010-06-09 北京航空航天大学 基于pci-e总线的直接存取数据传输控制装置
CN102549555B (zh) * 2009-10-07 2015-04-22 惠普发展公司，有限责任合伙企业 主机存储器的基于通知协议的端点高速缓存
US8650337B2 (en) * 2010-06-23 2014-02-11 International Business Machines Corporation Runtime determination of translation formats for adapter functions
KR101564520B1 (ko) * 2011-08-23 2015-10-29 후지쯔 가부시끼가이샤 정보 처리 장치 및 스케줄링 방법
US9002790B2 (en) * 2011-09-14 2015-04-07 Google Inc. Hosted storage locking
US9189441B2 (en) * 2012-10-19 2015-11-17 Intel Corporation Dual casting PCIE inbound writes to memory and peer devices
WO2014065878A1 (en) * 2012-10-22 2014-05-01 Venkatraman Iyer High performance interconnect physical layer
CN103885908B (zh) * 2014-03-04 2017-01-25 中国科学院计算技术研究所 一种基于外部设备可访问寄存器的数据传输系统及其方法

Also Published As

Publication number Publication date
TW201701165A (zh) 2017-01-01
US20160371222A1 (en) 2016-12-22
CN107980127A (zh) 2018-05-01
WO2016209733A1 (en) 2016-12-29
JP2018518777A (ja) 2018-07-12
EP3311279A1 (en) 2018-04-25
KR20180019595A (ko) 2018-02-26
BR112017027806A2 (pt) 2018-08-28

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MK4 Application lapsed section 142(2)(d) - no continuation fee paid for the application