WO2021155491A1

WO2021155491A1 - Data transfer with media transfer protocol (mtp) over universal serial bus (usb)

Info

Publication number: WO2021155491A1
Application number: PCT/CN2020/074259
Authority: WO
Inventors: Hongchao Guan; Feng JIAO
Original assignee: Qualcomm Incorporated
Priority date: 2020-02-04
Filing date: 2020-02-04
Publication date: 2021-08-12

Abstract

Systems and methods for data transfer with Media Transfer Protocol (MTP) over Universal Serial Bus (USB) contemplate breaking a USB read command and a vfs_write command into two distinct and separate threads as opposed to the common thread that an ANDROID operating system (OS) currently uses. An mtp_server thread may be split into two threads: one thread to add a file to mtp_storage and one thread to scan a media store to expedite refreshing the mtp_storage.

Description

DATA TRANSFER WITH MEDIA TRANSFER PROTOCOL (MTP) OVER UNIVERSAL SERIAL BUS (USB)

BACKGROUND

I. Field of the Disclosure

The technology of the disclosure relates generally to transferring files over a Universal Serial Bus (USB) bus using Media Transfer Protocol (MTP) .

II. Background

Computing devices, and particularly mobile computing devices, have become common in modern society. A variety of competing operating systems differentiate mobile computing devices. One of the leading operating systems is the ANDROID operating system (OS) based on a modified version of the LINUX kernel and other open source software. Many users connect mobile computing devices to a desktop computer through a Universal Serial Bus (USB) cable and connectors. Such connection may facilitate charging the mobile computing device as well as enable file transfers between the devices such as transferring photos or audio files. The ANDROID OS uses Media Transfer Protocol (MTP) to effectuate such file transfers.

SUMMARY OF THE DISCLOSURE

Aspects disclosed in the detailed description include systems and methods for data transfer with Media Transfer Protocol (MTP) over Universal Serial Bus (USB) . In particular, exemplary aspects contemplate breaking a USB read command and a vfs_write command into two distinct and separate threads as opposed to the common thread that an ANDROID operating system (OS) currently uses. In a further exemplary aspect, an mtp_server thread may be split into two threads: one thread to add a file to mtp_storage and one thread to scan a media store to expedite refreshing the mtp_storage. By splitting the USB read command and the vfs_write command into two threads, the USB read command no longer has to wait for the vfs_write command to finish before taking more data from the USB bus. Likewise, by splitting the file addition to the mtp_storage from the refresh command, the commands may be performed asynchronously, allowing more data to be retrieved more quickly. The net effect of these two changes is to improve transfer times.

In this regard in one aspect, a mobile computing device is disclosed. The mobile computing device includes an external bus receptacle configured to receive a male connector coupled to a cable housing an external bus. The mobile computing device also includes a bus circuit comprising a receiver circuit coupled to the external bus receptacle. The mobile computing device also includes a memory element. The mobile computing device also includes a multi-core processor communicatively coupled to the bus circuit and the memory element. The multi-core processor includes a first processing core comprising a first thread execution circuit. The multi-core processor also includes a second processing core comprising a second thread execution circuit. The multi-core processor also includes a thread management circuit configured to designate a read/write command for execution on the first processing core and a file system write command thread for execution on the second processing core.

In another aspect, a multi-core processor is disclosed. The multi-core processor includes a first processing core comprising a first thread execution circuit. The multi-core processor also includes a second processing core comprising a second thread execution circuit. The multi-core processor also includes a thread management circuit configured to designate a read/write command for execution on the first processing core and a file system write command thread for execution on the second processing core.

In another aspect, a method for handling operations in a multi-core processor is disclosed. The method includes receiving a read/write command from an external bus. The method also includes designating the read/write command to a first thread for execution by a first processing core within the multi-core processor. The method also includes receiving a file system write command. The method also includes designating the file system write command to a second thread for execution by a second processing core within the multi-core processor.

In another aspect, a method for handling operations in a multi-core processor is disclosed. The method includes receiving a file from an external bus. The method also includes designating adding the file to a memory element to a first thread for execution by a first processing core within the multi-core processor. The method also includes receiving a refresh command to refresh a media store. The method also includes designating the refresh command to a second thread for execution by a second processing core within the multi-core processor.

BRIEF DESCRIPTION OF THE FIGURES

Figure 1 illustrates a mobile computing device coupled to a desktop computing device through a Universal Serial Bus (USB) cable;

Figure 2 is a block diagram of USB hardware coupled to an application processor within the mobile computing device of Figure 1;

Figure 3 is a block diagram of an exemplary computing device having a multi-core processor with multiple threads from an application running on the multi-core processor;

Figures 4A and 4B illustrate conventional threads for file transfers using an ANDROID operating system over a USB bus;

Figure 5 illustrates an exemplary aspect of the present disclosure where a USB read command has a thread different from a concurrent vfs_write thread;

Figure 6 illustrates an exemplary aspect of the present disclosure where a Media Transfer Protocol (MTP) server thread has a thread different from a concurrent MTP database thread;

Figures 7A and 7B are flowcharts illustrating an exemplary process for splitting the threads for file access over a USB connection; and

Figure 8 is a block diagram of an exemplary processor-based system that can be the mobile computing device or the desktop computer of Figure 1.

DETAILED DESCRIPTION

With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration. ” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

In this regard, Figure 1 shows a mobile computing device 100 coupled to a desktop computer 102 having a keyboard 104, a mouse 106, and a display 108 via a USB cable 110. It should be appreciated that the mobile computing device 100 includes a USB receptacle 112 (generically an external bus receptacle) configured to receive a USB connector 114 (generically a male connector) on the USB cable 110. Similarly, the desktop computer 102 includes a USB receptacle 116 configured to receive a USB connector 118.

Figure 2 is a block diagram of certain elements of the mobile computing device 100. In particular, the mobile computing device 100 may include an application processor (AP) 200, which may be a multi-core processor that communicates with USB hardware (HW) 202 (generically a bus circuit) as well as system memory 204 and general memory 206. The USB HW 202 may interoperate with the receptacle 112 through a transmitter circuit (not shown) and a receiver circuit (not shown) as is well understood. The AP 200 may communicate with the USB HW 202 through an internal bus 208. Similarly, the AP 200 may communicate with the

memories

206 and 204 through

buses

210 and 212, respectively. In an exemplary aspect, the bus 210 or the bus 212 may be a Universal Flash Storage (UFS) bus. Further, the AP 200 may use an OS 214. In exemplary aspect, the OS 214 is an ANDROID OS. It should be appreciated that an OS such as the OS 214 may use one or more buffers within the AP 200. For example, a buffer 216 may be used for USB transfers and a buffer 218 may be used for MTP transfers. The

buffers

216 and 218 may be one megabyte (1 MB) each.

As noted, the AP 200 may be a multi-core processor as better illustrated in Figure 3, where application software 300 has multiple threads 302 (1) -302 (N) that operate on respective cores 304 (1) -304 (N) within the AP 200. A thread management circuit (not shown) in conjunction with the OS may be configured to designate which threads 302 (1) -302 (N) are routed to which processing cores 304 (1) -304 (N) for execution thereon. Note that there may be implementations where a core 304 (1) -304 (N) has more than one thread execution circuit (not shown) and multiple threads may operate on a single core. Likewise, there may be situations where the number of threads 302 (1) -302 (N) is less than the number of cores 304 (1) -304 (N) . For example, there may only be three active threads 302 (1) -302 (3) and four cores 304 (1) -304 (4) without departing from the scope of the present disclosure.

In the absence of the present disclosure, certain OSs may use a single thread to do multiple things. For example, a USB read command from the mobile computing device 100 to the desktop computer 102 may be in the same thread as the vfs_write command. Likewise, the mtp_receivefile command may be in the same thread as the scan media store command. The file copy throughput from a host PC such as the desktop computer to a mobile computing device such as a phone uses the MTP interface and is slow. For example, using an ANDROID OS, a single one gigabyte audio file using high-speed USB transfers at 29.68 MB/s. Likewise, when numerous small files are sent (e.g., photos) , similar delays occur. Testing shows that multiple small files bundled to about one gigabyte experience 22.78 MB/stransfer rates. These levels are substantially below USB highspeed (480 Mbs) or USB superspeed (5 gigabits/second (Gbs) ) . In the current LINUX USB MTP function driver (e.g., f_mtp. c) , two buffers (such as the

buffers

216, 218 of Figure 2) are used. One buffer is for data received from the USB bus and the other buffer is for data to be written to the file system. Both activities are in the same thread and both operations have to be executed in sequence. That means that when the USB data is drained, there may be a delay before another USB packet may be fetched from the USB hardware while the thread completes the vfs_write command. The vfs_write command may not be done because the UFS bus used to perform the vfs_write command may be operating at 16 Mbs. This results in unnecessary delays as explained with reference to Figures 4A and 4B.

In particular, Figure 4A illustrates how these two commands are combined in a single thread 400. The thread 400 may begin with an execution circuit in a processing core executing a USB read command 402 and then a vfs_write command 404 so long as there is data in the buffer (e.g., buffer 218) loading the buffer (e.g., buffer 216) . Only when the vfs_write command 404 is done (after some DELAY) , will the thread 400 advance to USB read completion 406 so that the thread 400 may retrieve the next USB packet 408.

Exemplary aspects of the present disclosure break this single slow thread into two separate threads to be executed by distinct thread execution circuits and reduce or eliminate the delays. However, the USB read/vfs_write command is not the only source of delays.

In an ANDROID OS, the MTP server (file mtpserver. cpp) may experience similar unnecessary delays. That is, after receipt of a file from the USB hardware and a write to a file system with vfs_write, the OS calls mtpdatabase with an endSendObject and a mediastore. scanfile command to refresh the mtpstorage. After the refresh, the mobile computing device will send a response to the desktop PC to send the object. The file addition and refresh may take 20+ milliseconds (ms) to complete and up to 70 ms when an audio or video file is received. This time may add a delay. When only one file is sent, this delay may not matter, but when many files are being transferred, this delay may affect the overall time it takes for the files to transfer.

Figure 4B illustrates how this refresh-related delay may occur. In particular, a single thread 420 begins with an mtp_receivefile 422 which adds the file to the mtpstorage 424. After adding the file, the thread execution circuit issues a scan media store command 426, which refreshes the mtpstorage. After the refresh (and some DELAY) , a response 428 is sent to the host PC so that the thread can receive 430 the next file.

Exemplary aspects of the present disclosure break this single slow thread into two separate threads to be executed by distinct thread execution circuits and reduce or eliminate the delays.

In this regard, Figure 5 shows a first exemplary aspect of spreading or breaking a single thread into two separate and

distinct threads

500A and 500B. Thread 500A works with a first buffer 216 to handle USB read requests independent of any vfs_write commands. Likewise, thread 500B works with a second buffer 218 to handle vfs_write commands without interleaving with any USB read request thread. In particular, the thread 500A checks to see if read buffer 216 is available 502, executes a USB read 504, and generates a USB read completion 506 so that another USB packet can be retrieved through a new read buffer check. The separate, distinct, and independent thread 500B executed by at least a different thread execution circuit if not a separate processing core executes the vfs_write command by checking to see if the buffer 218 has data 510 and then executing a vfs_write 512.

Similarly, Figure 6 shows spreading or breaking a single thread into two separate and

distinct threads

600A and 600B. Thread 600A is the mtp_server thread (generically a file storage thread) half of the original thread 420. In particular, the thread 600A has an mtp_receive_file 602, which adds the file to the mtpstorage 604. Based on this addition, a notification 606 is sent to the thread 600B and a new response to the host PC (i.e., desktop computer 102) is sent 608. Meanwhile thread 600B (generically a scan media storage thread) receives the notification 606 from the mtp_server thread 610 and initiates a scan of the media store/refreshes 612. By separating the refresh from the mtp_receive_file, the mtp_receive_file does not wait for the refresh and delay is reduced.

Processes

700, 750 associated with the present disclosure are provided with reference to Figures 7A and 7B. The process 700 illustrated in Figure 7A corresponds to the thread splitting of Figure 5, while the process 750 illustrated in Figure 7B corresponds to the thread splitting of Figure 6. In this regard, the process 700 begins by receiving a read/write command from an external bus (block 702) and designating the read/write command to a first thread 500A for execution by a first processing core within a multi-core processor (block 704) . The application processor 200 receives a file system write command (block 706) and designates the file system write command to a second thread 500B for execution by a second processing core within the multi-core processor (block 708) .

Similarly, the process 750 illustrated in Figure 7B begins by receiving a file from an external bus (block 752) and designating adding the file to a memory element to a first thread 600A for execution by a first processing core within a multi-core processor (block 754) . The application processor 200 receives a refresh command to refresh a media store (block 756) and designates the refresh command to a second thread 600B for execution by a second processing core within the multi-core processor (block 758) .

The systems and methods for data transfer with MTP over USB according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc. ) , a desktop computer, a personal digital assistant (PDA) , a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

In this regard, Figure 8 illustrates an example of a processor-based system 800 that can be the mobile computing device 100 or the desktop computer 102 illustrated in Figure 1. In this example, the processor-based system 800 includes one or more central processing units (CPUs) 802, each including one or more processors 804. The CPU 802 may have cache memory 806 coupled to the processor (s) 804 for rapid access to temporarily stored data. The CPU (s) 802 is coupled to a system bus 808 and can intercouple devices included in the processor-based system 800. As is well known, the CPU (s) 802 communicates with these other devices by exchanging address, control, and data information over the system bus 808. For example, the CPU (s) 802 can communicate bus transaction requests to a memory controller 810 as an example of a slave device.

Other devices can be connected to the system bus 808. As illustrated in Figure 8, these devices can include a memory system 812, one or more input devices 814, one or more output devices 816, one or more network interface devices 818, and one or more display controllers 820, as examples. The input device (s) 814 can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device (s) 816 can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device (s) 818 can be any devices configured to allow exchange of data to and from a network 822. The network 822 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN) , a wireless local area network (WLAN) , a wide area network (WAN) , a BLUETOOTH ^TM network, and the Internet. The network interface device (s) 818 can be configured to support any type of communications protocol desired. The memory system 812 can include a memory array 824.

The CPU (s) 802 may also be configured to access the display controller (s) 820 over the system bus 808 to control information sent to one or more displays 826. The display controller (s) 820 sends information to the display (s) 820 to be displayed via one or more video processors 828, which process the information to be displayed into a format suitable for the display (s) 826. The display (s) 826 can include any type of display, including, but not limited to, a cathode ray tube (CRT) , a liquid crystal display (LCD) , a plasma display, a light emitting diode (LED) display, etc.

Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium and executed by a processor or other processing device, or combinations of both. devices described herein may be employed in any circuit, hardware component, integrated circuit (IC) , or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP) , an Application Specific Integrated Circuit (ASIC) , a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration) .

The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM) , flash memory, Read Only Memory (ROM) , Electrically Programmable ROM (EPROM) , Electrically Erasable Programmable ROM (EEPROM) , registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

A mobile computing device comprising:

an external bus receptacle configured to receive a male connector coupled to a cable housing an external bus;

a bus circuit comprising a receiver circuit coupled to the external bus receptacle;

a memory element; and

a multi-core processor communicatively coupled to the bus circuit and the memory element, the multi-core processor comprising:

a first processing core comprising a first thread execution circuit;

a second processing core comprising a second thread execution circuit; and

a thread management circuit configured to designate a read/write command for execution on the first processing core and a file system write command thread for execution on the second processing core.
The mobile computing device of claim 1, wherein the external bus receptacle comprises a Universal Serial Bus (USB) receptacle.
The mobile computing device of claim 1, further comprising a Universal File System (UFS) bus coupling the multi-core processor to the memory element.
The mobile computing device of claim 1, wherein the multi-core processor comprises a first buffer configured to store data from the bus circuit and a second buffer configured to store data to write to a file system.
The mobile computing device of claim 4, wherein the first buffer may be drained and refilled with data from the bus circuit before the second buffer is fully drained.
The mobile computing device of claim 1, wherein the thread management circuit is further configured to designate a file storage thread for execution on the first processing core and designate a scan media storage thread for execution on the second processing core.
The mobile computing device of claim 1 selected from the group consisting of: an entertainment unit; a navigation device; a communications device; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a portable computer; a wearable computing device; a personal digital assistant (PDA) ; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a digital video player; a video player; a digital video disc (DVD) player; a drone; and a multicopter.
A multi-core processor comprising:

a first processing core comprising a first thread execution circuit;

a second processing core comprising a second thread execution circuit; and

a thread management circuit configured to designate a read/write command for execution on the first processing core and a file system write command thread for execution on the second processing core.
A method for handling operations in a multi-core processor, comprising:

receiving a read/write command from an external bus;

designating the read/write command to a first thread for execution by a first processing core within the multi-core processor;

receiving a file system write command; and

designating the file system write command to a second thread for execution by a second processing core within the multi-core processor.
A method for handling operations in a multi-core processor, comprising:

receiving a file from an external bus;

designating adding the file to a memory element to a first thread for execution by a first processing core within the multi-core processor;

receiving a refresh command to refresh a media store; and

designating the refresh command to a second thread for execution by a second processing core within the multi-core processor.