CN102375801A - Multi-core processor storage system device and method - Google Patents
Multi-core processor storage system device and method Download PDFInfo
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- CN102375801A CN102375801A CN2011102426984A CN201110242698A CN102375801A CN 102375801 A CN102375801 A CN 102375801A CN 2011102426984 A CN2011102426984 A CN 2011102426984A CN 201110242698 A CN201110242698 A CN 201110242698A CN 102375801 A CN102375801 A CN 102375801A
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Abstract
The invention discloses a multi-core processor storage system device, which is used as a part of a multi-core processor system structure for finishing the quick access operation to instruction data in the running process of the processor system. The storage system device comprises a master storage device, an instruction caching device, a data caching device, an intermediate data caching array device and a multi-core processor array device, wherein the master storage device is used for storing instruction codes and data; the instruction caching device is used for reading the instruction codes from the master storage device and caching the instruction codes; the data caching device is used for reading data from the master storage device and caching the data, receiving result data output by a multi-core processor array, storing the received data, and simultaneously writing back the result data in the master storage device; the intermediate data caching array device is used for caching the intermediate data generated by the multi-core processor array device in a computation process; and the multi-core processor array device is used for reading the instruction codes from the instruction caching device, reading data from the data caching device, executing the instruction codes so as to execute data computation, and writing or reading the intermediate computation data via an intermediate data caching array.
Description
Technical field
The present invention relates to microprocessor and field of computer, specifically, involvement aspect is to the polycaryon processor storage system architecture.
Background technology
Along with the speed of processor improves constantly, the development of polycaryon processor parallel computation simultaneously makes the efficient of calculating constantly strengthen, simultaneously, also to the data access efficiency require increasingly high.Because the efficient of data access is very big to the polycaryon processor performance impact, the efficient that therefore improves the data access of computing machine is even more important.
In traditional polycaryon processor storage system (like Fig. 3), the overall procedure of its operation (like Fig. 4) is not distinguished calculating employed data, so the access procedure of intermediate data and net result data is identical.In traditional polycaryon processor storage system each time the intermediate computations data all write back main storage means, all to read next time the process of the data of calculating each time from main storage means, make the The whole calculations process become complicated and loaded down with trivial details, reduced the efficient of access.
Summary of the invention
The present invention proposes a kind of polycaryon processor storage system device, is used for making up polycaryon processor storage system system more efficiently.
Polycaryon processor storage system device bag of the present invention: main storage means, caching device, intermediate data array cache device; Bus unit; The polycaryon processor array apparatus, main storage means wherein, caching device; Polycaryon processor array apparatus, intermediate data array cache device connect through bus unit successively.
Wherein, said main storage means is used for store instruction codes and data;
Said caching device comprises instruction cache device and data high-speed buffer-store device, said instruction cache device reading command code and buffer memory from main storage means; Said data high-speed buffer-store device, this device reading of data and buffer memory from main storage means receive result data and buffer memory that the polycaryon processor array apparatus is exported, simultaneously result data are write back in the main storage means;
Said intermediate data array cache device, the intermediate data of buffer memory polycaryon processor array apparatus in computation process;
Said polycaryon processor array apparatus; From said instruction cache device reading command code, from said data high-speed buffer-store device reading of data, the execution command code carries out data computation; And use said intermediate data array cache, write or read the intermediate computations data;
Said bus unit comprises: intermediate data array cache device access bus, and said polycaryon processor array apparatus is through this bus access intermediate data cache blocks;
The caching device access bus, said polycaryon processor array apparatus passes through the said data high-speed buffer-store device of this bus access, and passes through this bus from said instruction cache device reading command code;
Main storage means access bus, said data high-speed buffer-store device are through the said main storage means of this bus access, and said instruction cache device passes through this bus from said main storage means reading command code.
Described intermediate data array cache device comprises a plurality of intermediate data cache blocks, and said intermediate data cache blocks is the storer that is used to store intermediate data.
Described polycaryon processor array apparatus comprises a plurality of processor cores, and its each processor core is single processor unit.
Said instruction cache device is from said main storage means, and acquisition in advance needs the instruction code of execution, and said data high-speed buffer-store device is from said main storage means simultaneously; The data that acquisition in advance needs, then, said polycaryon processor array apparatus is from said instruction cache device and said data high-speed buffer-store device; Reading command code and data are carried out and are calculated, and the intermediate computations data are write said intermediate data array cache device; Then read desired data from said intermediate data array cache device; From said instruction cache device reading command code, continue to calculate, so circulation simultaneously; Until calculating the net result data; And the net result data are write said data high-speed buffer-store device, last, said data high-speed buffer-store device writes back the net result data in the said main storage means.
Operation steps according to polycaryon processor storage means of the present invention is as shown in Figure 1.Concrete grammar and characteristic are may further comprise the steps:
Step 1: caching device reads instruction code and data in the main storage means;
Step 2: the polycaryon processor array reads instruction code and data in the caching device;
Step 3: the polycaryon processor array is carried out and is calculated;
Step 4: calculation result data is written in the data high-speed buffer-store device;
Step 5, caching device writes back to the net result data in the main storage means.
Wherein, in step 1, said caching device is instruction cache device and data high-speed buffer-store device, and it further comprises step:
Step 1.1 reads required instruction code in the instruction cache device in advance from main storage means;
Step 1.2 reads required data in the data high-speed buffer-store device from main storage means in advance;
Said step 2 further comprises step:
Step 2.1, polycaryon processor array apparatus reading command code fast from the instruction cache device;
Step 2.2, when the polycaryon processor array apparatus need use in the main storage means data, reading of data fast from data high-speed buffer-store device;
Wherein, in said step 3, the polycaryon processor array apparatus is carried out when calculating, and can also comprise following steps:
Step 3.1, the intermediate data that calculates writes in the intermediate data array cache device fast;
Step 3.2, polycaryon processor array apparatus read from middle cache data array device and calculate required intermediate data once more, simultaneously from instruction cache device reading command code; Continue to carry out and calculate,, then finish to calculate if calculate the net result data; Get into step 4; Otherwise return step 3.1, computed information is write intermediate data array cache device fast as intermediate data, and then execution in step 3.2;
In the described step 2, described polycaryon processor array apparatus comprises a plurality of processor cores, and each processor core is single processor unit.
In the described step 3.1, described intermediate data array cache device comprises a plurality of intermediate data cache blocks; Intermediate data writes in the intermediate data cache blocks through intermediate data array cache device access bus.
The present invention is the interim character that exists according to the intermediate computations data, has saved the intermediate computations data are write back main storage means and read the process of main storage means once more, has promoted access efficiency and speed, has improved the efficient of processor.
Description of drawings
With reference to following accompanying drawing with easy to understand the present invention more:
Storage system overview flow chart for the present invention's proposition shown in Figure 1;
Shown in Figure 2 for being used to realize the structured flowchart of storage system device of the present invention;
Shown in Figure 3 is the structured flowchart of traditional storage system;
Shown in Figure 4 is traditional storage system overview flow chart;
The structured flowchart of Fig. 5 intermediate data array cache device;
The structured flowchart of Fig. 6 polycaryon processor array.
Embodiment
Polycaryon processor storage system device of the present invention (like Fig. 2) comprising: main storage means, caching device, intermediate data array cache device, bus unit, polycaryon processor array apparatus; Main storage means wherein; Caching device; Polycaryon processor array apparatus, intermediate data array cache device connect through bus unit successively.
Wherein, described main storage means is used for store instruction codes and data;
Described caching device comprises instruction cache device and data high-speed buffer-store device, and the instruction cache device is reading command code and buffer memory from main storage means; And data high-speed buffer-store device reading of data and buffer memory from main storage means receive result data and buffer memory that the polycaryon processor array apparatus is exported, simultaneously result data are write back in the main storage means;
Described intermediate data array cache device comprises a plurality of intermediate data cache blocks, and is as shown in Figure 5, intermediate data cache blocks 1, intermediate data cache blocks 2 ..., intermediate data cache blocks M, these intermediate data cache blocks are the storeies that are used to store intermediate data; Intermediate data array cache device can the intermediate data of buffer memory polycaryon processor array apparatus in computation process;
Described polycaryon processor array apparatus comprises a plurality of processor cores, and is as shown in Figure 6, processor core 1, processor core 2 ..., processor core N, its each processor core is single processor unit.The polycaryon processor array apparatus is from said instruction cache device reading command code; From said data high-speed buffer-store device reading of data; The execution command code carries out data computation, and uses said intermediate data array cache, writes or read the intermediate computations data;
Described bus unit (as shown in Figure 2) comprising: intermediate data array cache device access bus, and said polycaryon processor array apparatus is through this bus access intermediate data cache blocks; The caching device access bus, said polycaryon processor array apparatus passes through the said data high-speed buffer-store device of this bus access, and passes through this bus from said instruction cache device reading command code; Main storage means access bus, said data high-speed buffer-store device are through the said main storage means of this bus access, and said instruction cache device passes through this bus from said main storage means reading command code.
Apparatus of the present invention are implemented in the following manner, like Fig. 2, Fig. 5, shown in Figure 6:
At first; As shown in Figure 2; Said instruction cache device is through the main storage means access bus instruction code that acquisition in advance need be carried out from said main storage means, and said data high-speed buffer-store device is through the main storage means access bus data that acquisition in advance needs from said main storage means simultaneously;
Then; Said polycaryon processor array apparatus passes through caching device access bus reading command code and data from said instruction cache device and said data high-speed buffer-store device respectively; Processor core 1 (as shown in Figure 6) calculates data according to the instruction code that reads, and through intermediate data array cache device access bus the intermediate computations data is write in the said intermediate data array cache device in the intermediate data cache blocks 1 (as shown in Figure 5);
Then; Processor core 2 (as shown in Figure 6) reads computing desired data next time through intermediate data array cache device access bus intermediate data cache blocks 1 from said intermediate data array cache device in the said polycaryon processor array apparatus; Read the required instruction code of computing next time through the caching device access bus from said instruction cache device simultaneously; According to the instruction code that obtains data continue are calculated, the intermediate computations data are write in the said intermediate data array cache device in the intermediate data cache blocks 2;
Next; Processor core 3 reads computing desired data next time through intermediate data array cache device access bus intermediate data cache blocks 2 from said intermediate data array cache device in the said polycaryon processor array apparatus; Read the required instruction code of computing next time through the caching device access bus from said instruction cache device simultaneously; According to the instruction code that obtains data continue are calculated, the intermediate computations data are write in the said intermediate data array cache device in the intermediate data cache blocks 3;
So circulation until calculating the net result data, and writes said data high-speed buffer-store device with the net result data through the caching device access bus; At last, said data high-speed buffer-store device writes back the net result data in the said main storage means through the main storage means access bus.
Compared to traditional polycaryon processor storage system; Can obviously find out from both overall procedures; Polycaryon processor storage system device of the present invention; Save the process that the intermediate computations data is write back main storage means, also saved the process that reads main storage means once more, significantly improved the efficient of access.
Illustrate polycaryon processor memory storage of the present invention method of operating, as shown in Figure 1 may further comprise the steps:
Step 1: caching device reads instruction code and data in the main storage means;
In advance required instruction code is read from main storage means in the instruction cache device through the main storage means access bus, from main storage means read in data high-speed buffer-store device through the main storage means access bus required data in advance;
Step 2: the polycaryon processor array apparatus reads instruction code and data in the caching device;
Comprise a plurality of processor cores in polycaryon processor array apparatus (like Fig. 6) inside, each processor core is single processor unit; Processor core 1 reads the instruction code that needs respectively through the caching device access bus from the instruction cache device, from data high-speed buffer-store device, read the data that need;
Step 3: the polycaryon processor array apparatus is carried out and is calculated;
Step 3.1, the intermediate data that calculates writes in the intermediate data array cache device fast;
After processor core 1 is carried out and is calculated; Assumed calculation draws intermediate data X; Intermediate data X is write in the intermediate data array cache device through intermediate data array cache device access bus; Comprise a plurality of intermediate data cache blocks in intermediate data array cache device (like Fig. 5) inside, so intermediate data X writes intermediate data cache blocks 1 through intermediate data array cache device access bus;
Step 3.2; Processor core 2 reads the instruction code that calculating once more needs through the caching device access bus from the instruction cache device; From middle metadata cache piece 1, read intermediate data X through intermediate data array cache device access bus simultaneously; And use X to continue to calculate, obtain data Y;
Step 4: processor core 2 reads the instruction code that stop to calculate through the caching device access bus from the instruction cache device, then data Y as the net result data, be written in the data high-speed buffer-store device;
Step 5, caching device is written to the net result data in the main storage means;
Data high-speed buffer-store device writes back to the net result data Y in the main storage means through the main storage means access bus again.
Claims (10)
1. a polycaryon processor storage system device is characterized in that comprising: main storage means, caching device; Intermediate data array cache device, bus unit, polycaryon processor array apparatus; Main storage means wherein; Caching device, polycaryon processor array apparatus, intermediate data array cache device connect through bus unit successively.
2. polycaryon processor storage system device according to claim 1, wherein,
Said main storage means is used for store instruction codes and data;
Said caching device comprises instruction cache device and data high-speed buffer-store device, said instruction cache device reading command code and buffer memory from main storage means; Said data high-speed buffer-store device is reading of data and buffer memory from main storage means, receives the result data and the buffer memory of polycaryon processor array apparatus output, simultaneously result data is write back in the main storage means;
Said intermediate data array cache device, the intermediate data of buffer memory polycaryon processor array apparatus in computation process;
Said polycaryon processor array apparatus; From said instruction cache device reading command code, from said data high-speed buffer-store device reading of data, the execution command code carries out data computation; And use said intermediate data array cache, write or read the intermediate computations data;
Said bus unit comprises: intermediate data array cache device access bus, caching device access bus, main storage means access bus.
3. polycaryon processor storage system device according to claim 2, wherein,
Described intermediate data array cache device access bus, said polycaryon processor array apparatus is through this bus access intermediate data cache blocks;
Described caching device access bus, said polycaryon processor array apparatus passes through the said data high-speed buffer-store device of this bus access, and through the said instruction cache device of this bus reading command code;
Described main storage means access bus, said data high-speed buffer-store device are through the said main storage means of this bus access, and said instruction cache device passes through this bus from said main storage means reading command code.
4. polycaryon processor storage system device according to claim 2, wherein, described intermediate data array cache device comprises a plurality of intermediate data cache blocks, said intermediate data cache blocks is the storer that is used to store intermediate data.
5. polycaryon processor storage system device according to claim 2, wherein, described polycaryon processor array apparatus comprises a plurality of processor cores, its each processor core is single processor unit.
6. a polycaryon processor storage means is characterized in that, described polycaryon processor storage means may further comprise the steps:
Step 1: caching device reads instruction code and data in the main storage means;
Step 2: the polycaryon processor array reads instruction code and data in the caching device;
Step 3: the polycaryon processor array is carried out and is calculated;
Step 4: calculation result data is written in the data high-speed buffer-store device;
Step 5, caching device writes back to the net result data in the main storage means.
7. polycaryon processor storage means according to claim 6, wherein, in the described step 1, said caching device is instruction cache device and data high-speed buffer-store device, it further comprises step;
Step 1.1 reads required instruction code in the instruction cache device in advance from main storage means;
Step 1.2 reads required data in the data high-speed buffer-store device from main storage means in advance.
8. polycaryon processor storage means according to claim 6, wherein, described step 2 further comprises step:
Step 2.1, polycaryon processor array apparatus reading command code fast from the instruction cache device;
Step 2.2, when the polycaryon processor array apparatus need use in the main storage means data, reading of data fast from data high-speed buffer-store device.
9. polycaryon processor storage means according to claim 6, wherein, described step 3, the polycaryon processor array apparatus is carried out when calculating, and comprises following steps:
Step 3.1, the intermediate data that calculates writes in the intermediate data array cache device fast;
Step 3.2, polycaryon processor array apparatus read from middle cache data array device and calculate required intermediate data once more, simultaneously from instruction cache device reading command code; Continue to carry out and calculate,, then finish to calculate if calculate the net result data; Get into step 4; Otherwise return step 3.1, computed information is write intermediate data array cache device fast as intermediate data, and then execution in step 3.2.
10. polycaryon processor storage means according to claim 6, wherein,
In the described step 2, described polycaryon processor array apparatus comprises a plurality of processor cores, and each processor core is single processor unit;
In the described step 3.1, described intermediate data array cache device comprises a plurality of intermediate data cache blocks; Intermediate data writes in the intermediate data cache blocks through intermediate data array cache device access bus.
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| CN103995796A (en) * | 2014-05-29 | 2014-08-20 | 河南中医学院 | Symphony orchestra type multi-core CPU and multi-internal-storage computer system |
| CN110321204A (en) * | 2018-03-31 | 2019-10-11 | 北京深鉴智能科技有限公司 | Computing system, hardware accelerator management method and device and storage medium |
| CN112558861A (en) * | 2020-09-29 | 2021-03-26 | 北京清微智能科技有限公司 | Data loading and storing system and method for multi-core processor array |
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| WO2023241417A1 (en) * | 2022-06-14 | 2023-12-21 | 北京有竹居网络技术有限公司 | Processor, method for data processing, device, and storage medium |
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Application publication date: 20120314 |