AU2007345826C1 - Forced commutated inverter apparatus - Google Patents

Description

WO 2008/093429 PCT/JP2007/051848 1 DESCRIPTION FORCED COMMUTATED INVERTER APPARATUS TECHNICAL FIELD The present invention relates to a forced commutated inverter 5 apparatus, and in particular, to a forced commutated high power voltage source inverter apparatus, which includes gate turn-off devices such as GCTs, IEGTs or IGBTs, freewheel diodes, and a clamp circuitry. BACKGROUND ART Forced commutated high power voltage source inverter apparatuses 10 each include gate turn-off devices, freewheel diodes, a clamp circuitry, and a DC-supply storage unit such as a bank of capacitors. Depending on the application, various kinds of basic circuitry configurations are applied such as a chopper configuration, a 2-level configuration, a 3-level configuration, and a multi-level configuration. 15 In an on-state, practical high voltage freewheel diodes each having blocking capability such as 4.5 kV or 6 kV accumulate a significant amount of charge carriers. Then, those charge carriers need to be extracted by a reverse current, before the blocking state is obtained. Due to such a reverse recovery current, such diodes will present 20 relatively low impedance for a short time span after initiating the reverse condition. In order to avoid any excessive current, some type of current control therefore needs to be applied. Basically, two types of reverse recovery current control by passive elements have been proposed as follows: 25 (a) current control by linear anode reactors; and (b) current control by saturable cores.

WO 2008/093429 PCT/JP2007/051848 2 A reverse recovery current control of prior art by linear anode reactor will be described hereinafter which is disclosed in the following patent documents: (a) European patent laid-open publication No. EP-0776083-A2 5 (referred to as a first patent document hereinafter); (b) U.S. patent No. 5768114, which is a family of the first patent document; and (c) Japanese patent No. JP-3749580-B2, which is another family of the first patent document. 10 The first patent document discloses snubber-less reverse recovery control by a linear anode reactor, and a prior art forced commutated high power voltage source chopper circuitry using a linear anode reactor. The chopper circuitry includes a DC-link capacitor fed through input lines, a switch arm including a gate turn-off device and a freewheel diode, an 15 anode reactor, and a clamp circuitry including a clamp diode. In an experimental example of the chopper circuitry, after decrease in the current flowing in the freewheel diode to zero, the freewheel diode then exhibits reverse recovery, namely, charge carriers in the freewheel diode still maintain a high conductivity, while the anode current turns to 20 the reverse direction. As a consequence, the voltage across the freewheel diode stays close to zero for a fraction of time. Thereafter, the voltage across the freewheel diode can fall to approach the value of the DC-link voltage. Namely, due to the inductance of the anode reactor, the anode current flowing in the freewheel diode continues increasing, and then, the 25 same current can commutate to the clamp circuitry. In this case, the voltage across the freewheel diode stays close to the value of the DC-link WO 2008/093429 PCT/JP2007/051848 3 capacitor, and the freewheel diode can reduce its anode current. In a typical anode voltage versus anode current characteristics of the above used freewheel diode, for each forward current thereof, the reverse voltage does approach the highest value, when also the anode 5 current comes to the highest value. Then, high apparent reverse recovery power is created in the diode at elevated anode voltage, thus causing a high level of reverse recovery stress. Moreover, such an apparent reverse recovery power does decreases only slightly by reducing the forward current. With a typical diode, a reduction of the forward current from 10 6000 A to 100 A, that is, by a factor of 60, may reduce the apparent reverse recovery power by a value as little as a factor of 2. As a consequence, the freewheel diode under such a condition will be most prone to failure at the reverse recovery from a small level of the forward current. 15 Next, a reverse recovery current control by a saturable core will be described hereinafter, which is disclosed in the following patent documents: (a) Japanese patent No. JP-3745561-B2 (referred to as a second patent document hereinafter); and 20 (b) U.S. patent No. 6392907, which is a family of the second patent document. The second patent document discloses a forced commutated inverter using the reverse recovery control by saturable cores. In the inverter, one or two of the saturable cores will cut the current flowing into 25 at least one of two DC-link capacitors. During the reverse recovery of a freewheel diode, the reverse recovery current is set solely by a clamp WO 2008/093429 PCT/JP2007/051848 4 network including a clamp capacitor, a clamp diode, and clamp resistors. Generally, low loss saturable cores are selected for the present application. In a magnetic flux B to strength H of electric field characteristic of the saturable core, the saturable core acts upon a small 5 magnetic field, and switching is caused between the two extreme saturation states of the maximum magnetic flux Bma and the minimum magnetic flux Bmin. This leads to generation with a small loss. In this way, a large amount of energy storage in an anode reactor has been avoided. However, another following problem has been introduced with 10 introduction of such saturable cores, in particular, a prior art 3-phase 3 level inverter including saturable cores. When the voltage of the DC-link capacitor is charged by a current from another phase, then the saturable cores of the 3-level inverter receive a current flow based on displacement currents flowing into the clamp capacitors, and then, these saturable 15 cores are switched over to the corresponding saturation state. In this way, the saturable cores may be set to a state just opposite to what is required to protect a freewheel diode at a reverse recovery. Then, a reverse recovery current flowing in the freewheel diode will rise with a high value of dI/dt, most probably causing failure in the freewheel diode. 20 The high power inverter circuitry using linear anode reactors has a problem of using a large inductance to satisfy the requirements of typical high voltage freewheel diodes. During every switching cycle, such reactors store and release a considerable amount of energy, which gives a significant contribution to the total loss of the inverter. In addition the 25 high power inverter circuitry using linear anode reactors gives a purely inductive load on the high voltage freewheel diodes. Such a purely 5 inductive load puts the highest stress on these freewheel diodes. Most severe stress situations then are observed at a small load current, thus impeding the need for undesirably high inductor values. The prior art high power inverters each using saturable cores have cores with two 5 clearly defined saturation states. As a consequence, high power converters using fast turn on devices such as GCTs, IGBTs or IEGTs then have a risk of reverse recovery overloading due to improper setting of core saturation state. A need therefore exists to provide a forced commutated inverter apparatus capable of performing a well-defined operation under almost all conditions in a real 10 application with a reliable control of the diode reverse recovery current. SUMMARY OF THE INVENTION It is an object of the present invention to substantially overcome or at least ameliorate one or more of the above disadvantages. According to one aspect of the present invention, there is provided a forced is commutated high power inverter apparatus having a maximum rated output current Wit, which includes at least one DC-link capacitor, at least one anode leakage inductance, at least one switch arm, at least one clamp circuitry, and at least one saturable core unit. The DC-link capacitor has a voltage ripple characterized by a maximum value dVm of an absolute value of a rising rate dVDc/dt, which satisfies a relation of -dVm _ dVDc/dt < 20 dVm, and the anode leakage inductance is connected in series with the DC-link capacitor. The switch arm includes a series connection circuitry of at least one gate turn-off device and at least one freewheel diode, and the clamp circuitry includes at least one clamp capacitor, at least one clamp diode, and at least one clamp voltage reset circuitry which includes at least one resistor.

WO 2008/093429 PCT/JP2007/051848 6 The forced commutated high power inverter apparatus is characterized in that the saturable core unit has one of a linear saturation characteristic and a gradual saturation characteristic, each having a saturation current Isat, and the saturation current Isat is set to be larger 5 than a displacement current created by a rising rate of dVm, with a capacitance C3 1 of at least one clamp capacitor, so as to satisfy a relation of the following equation: IRout > Isat > C 3 1 x dVm. In the above-mentioned forced commutated high power inverter 10 apparatus, since a saturable core unit is used in the forced commutated inverter apparatus, which has incorporated a well-defined reset state and force, a well-defined operation can be performed under almost all conditions in a real application. As a consequence, reliable control of diode reverse recovery current can be performed. 15 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a circuitry diagram showing a configuration of a forced commutated high power chopper circuitry according to a first preferred embodiment of the present invention. Fig. 1B is a circuitry diagram showing a configuration of a forced 20 commutated 2-level high power inverter according to the first preferred embodiment of the present invention. Fig. 1C is a circuitry diagram showing a configuration of a forced commutated 3-level high power inverter according to the first preferred embodiment of the present invention. 25 Fig. 1D is a graph showing an electrical characteristic of a voltage time integral IVdt to a current I of each of saturable core units 5a, 5b and WO 2008/093429 PCT/JP2007/051848 7 5c shown in Figs. 1A, 1B and 1C, and showing a saturation current Isat thereof. Fig. 2A is a graph showing an electrical characteristic of a voltage time integral J Vdt to a current I of each of saturable core units 5a, 5b and 5 5c shown in Figs. 1A, lB and 1C while defining a saturation voltage time integral I Vdtsat thereof according to a second preferred embodiment of the present invention. Fig. 2B is a graph showing a relation between a reverse recovery charge Qrr and a forward current I flowing in a typical high voltage high 10 power silicon diode at an elevated junction temperature. Fig. 2C is a waveform chart showing (a) voltages V5a and Vsb of the saturable voltage units 5a and 5b, (b) a normalized magnetic flux F5a and Fsb thereof, and (c) a voltage V 22 and a current 122 of a diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an output current 15 Iout = 100 A. Fig. 2D is a waveform chart showing (a) the voltages Va and V5b of the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and F5b thereof, and (c) the voltage V 22 and the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an 20 output current Lout = 400 A. Fig. 2E is a waveform chart showing (a) the voltages V 5 a and Vsb of the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and F5b thereof, and (c) the voltage V 2 2 and the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an 25 output current lout = 1000 A. Fig. 2F is a waveform chart showing (a) the voltages Vsa and Vsb of WO 2008/093429 PCT/JP2007/051848 8 the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and F5b thereof, and (c) the voltage V 22 and the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an output current Iout = 3000 A. 5 Fig. 2G is a waveform chart showing (a) the voltages V 5 a and VSb of the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and Fsb thereof, and (c) the voltage V 22 and the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an output current Iout = 6000 A. 10 Fig. 2H is a graph showing an estimated relation of an anode voltage to an anode current of the diode 22 for each turn-off with a parameter of output current Iout. Fig. 21 is a graph showing an estimated relation of a reverse recovery power to an anode voltage of the diode 22 with a parameter of output 15 current Iout. Fig. 2J is a graph showing an estimated relation of a stress reverse recovery power to an output current lout of the diode 22 for various circuitry configurations and respective settings of the saturation voltage time integral JVdtsat 20 Fig. 3A is a block diagram showing the saturable core unit 5a according to the third preferred embodiment of the present invention. Fig. 3B is a perspective view showing an appearance of the saturable core unit 5a of Fig. 3A. Fig. 4 is a circuitry diagram showing a configuration of a forced 25 commutated high power inverter according to a fourth preferred embodiment of the present invention.

WO 2008/093429 PCT/JP2007/051848 9 Fig. 5A is a circuitry diagram showing a configuration of a saturable core unit 5a for use in a forced commutated high power inverter according to a fifth preferred embodiment of the present invention. Fig. 5B is a waveform chart of a first part in an unbalanced case 5 showing (a) a current Isa of the saturable core unit 5a, and (b) a current 171 of an inductance 71 of Fig. 5A and a normalized magnetic flux F5i of a saturable inductor 51 of Fig. 5A. Fig. 5C is a waveform chart of a second part in the unbalanced case showing (a) the current Ia of the saturable core unit 5a, and (b) the 10 current 171 of the inductance 71 of Fig. 5A and the normalized magnetic flux F 5 i of the saturable inductor 51 of Fig. 5A. Fig. 5D is a waveform chart of a first part in a preferred case showing (a) the current Ia of the saturable core unit 5a, and (b) the current 171 of the inductance 71 of Fig. 5A and the normalized magnetic 15 flux F5 1 of the saturable inductor 51 of Fig. 5A. Fig. 5E is a waveform chart of a second part in the preferred case showing (a) the current Isa of the saturable core unit 5a, and (b) the current 171 of the inductance 71 of Fig. 5A and the normalized magnetic flux F5i of the saturable inductor 51 of Fig. 5A. 20 Fig. 6A is a circuitry diagram showing a configuration of a forced commutated high power inverter according to a sixth preferred embodiment of the present invention. Fig. 6B is a waveform chart showing a voltage V 5 a of the saturable core unit 5a of Fig. 6A, and a voltage V 2 2 and a current 122 of a freewheel 25 diode 22 of Fig. 6A when a clamp circuitry 3 includes a clamp resistor 331 with a typical clamp resistor's leakage inductance 33 1a of 1.5 pH.

WO 2008/093429 PCT/JP2007/051848 10 Fig. 6C is a waveform chart showing the voltage Vsa of the saturable core unit 5a of Fig. 6A, and the voltage V 22 and the current 122 of the freewheel diode 22 of Fig. 6A when enhancing the diode's reverse recovery current right in the beginning, and later adding a damping to the clamp 5 resistor's leakage inductance 33 la. Fig. 7A is a circuitry diagram showing a configuration of a forced commutated high power inverter according to a seventh preferred embodiment of the present invention. Fig. 7B is a waveform chart in the case without any delay core 336, 10 showing a voltage V5a of the saturable core unit 5a, a voltage V5b of the saturable core unit 5b, a voltage V 2 2 and a current 122 of the freewheel diode 22, and a current 133 of a clamp voltage reset circuitry 33. Fig. 7C is a waveform chart in the case with the delay core 336, showing the voltage V 5 a of the saturable core unit 5a, the voltage V5b of the 15 saturable core unit 5b, the voltage V 22 and the current 122 of the freewheel diode 22, and the current Ina of the clamp voltage reset circuitry 33. BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments will be described with reference to drawings attached herewith. Components or elements similar to each other are 20 denoted by the same reference numericals. FIRST PREFERRED EMBODIMENT Fig. 1A shows a configuration of a forced commutated high power chopper circuitry according to a first preferred embodiment of the present invention, Fig. 1B shows a configuration of a forced commutated 2-level 25 high power inverter according to the first preferred embodiment of the present invention, Fig. 1C shows a configuration of a forced commutated WO 2008/093429 PCT/JP2007/051848 11 3-level high power inverter according to the first preferred embodiment of the present invention, and Fig. 1D shows an electrical characteristic of a voltage time integral JVdt to a current I of each of saturable core units 5a, 5b and 5c shown in Figs. 1A, 1B and 1C, and shows a saturation current 5 Isat thereof. CHOPPER CIRCUITRY Referring to Fig. 1A, the chopper circuitry according to the present preferred embodiment has input terminals Ti and T2, and an output terminal T1 1. The chopper circuitry includes a DC-link capacitor 11, a 10 switch arm 2, a clamp circuitry 3, an anode leakage inductor 41, a saturable core unit 5a, and a controller 91. The switch arm 2 includes a serial circuitry of a gate turn-off device 21 such as a GCT, an IEGT, or an IGBT,. and a freewheel diode 22. The clamp circuitry 3 includes a clamp capacitor 31, a clamp diode 32, and a clamp voltage reset circuitry 33 15 which includes a clamp resistor 331. The controller 91 periodically generates and outputs a gate control voltage signal to a gate of the gate turn-off device 21. In the chopper circuitry, the DC-link capacitor 11 is connected between the input terminals T1 and T2. The input terminal T1 is 20 connected through the anode leakage inductance 41 to one end of the switch arm 2 and one end of the clamp circuitry 3. On the other hand, the input terminal T2 is connected through the saturable core unit 5a to another end of the switch arm 2 and another end of the clamp circuitry 3. In this case, the saturable core unit 5a can control a reverse 25 recovery current flowing from the freewheel diode 22 to the DC-link capacitor 11. The anode leakage inductance 41 may be a separate WO 2008/093429 PCT/JP2007/051848 12 element, which is designed to limit the current from the DC-link capacitor 11 through the gate turn-off device 21, the freewheel diode 22, and the saturable core unit 5a. However, the anode leakage inductance 41 may be also reduced to a very low value of a bus leakage inductance. 5 The operation of the chopper circuit will be described as follows. State 1: Gate turn-off device 21 being in on-state With the gate turn-off device 21 in on-state, a load current flows from the input terminal Ti which is so-called "P(Positive) -terminal" through the anode leakage inductance 41 and the gate turn-off device 21 10 to the output terminal T 11. Then, the freewheel diode 22 is blocking. Depending on the charge in the clamp capacitor 31, a current may flow from the anode leakage inductance 41 through the clamp capacitor 31, then through a parallel connection circuitry of the clamp diode 32 and the clamp voltage reset circuitry 33, and further through the saturable core 15 unit 5a, to the input terminal T2 which is so-called "N(Negative)-terminal", until the voltage across the clamp capacitor 31 has become equal to the voltage across the DC-link capacitor 11. Thereafter, the voltage across the saturable core unit 5a will become zero, and the current flow is stopped. According to Fig. 1D, the saturable core unit 5a then has reached a near 20 center position of its characteristic of Fig. 1D corresponding to a so-called B-H curve. In this way, a complete reset of the saturable core unit 5a and the clamp capacitor 31 is achieved. State 2: Gate turn-off device 21 turning off When the gate turn-off device 21 turns off, then some over voltage 25 will appear across its terminals because of the anode leakage inductance 41. The clamp circuitry 3 is closely wired into the circuitry having small WO 2008/093429 PCT/JP2007/051848 13 parasitic inductance, such as 200 nH or 400 nH. The current flowing from the gate turn-off device 21 then will commutate to the clamp circuitry 3, where the same current mainly flows in the clamp capacitor 31 and the clamp diode 32. Then, the same current flows in the freewheel 5 diode 22 and outputs through the output terminal T1 1. State3: Steady state under gate turn-off device 21 being turned off As the output current Iout continues to flow, the clamp capacitor 31 will charge to an elevated level, causing a negative potential at the output terminal T 11. The saturable core unit 5a will receive and accumulate the 10 same voltage accordingly, to generate a voltage time integral JVdt, and this leads to a conduct current according to Fig. 1D. If the load output current Iout is larger than a saturation current Isat of the saturable core unit 5a as shown in Fig. 1D, then, the saturable core unit 5a will become a saturation state, and switch the voltage across its terminals into zero. If 15 lout < Isat, then the saturable core unit 5a will stay in a linear and non saturated region of the characteristic of Fig. 1D, and show an equivalent inductance as its circuitry, but also pull the voltage across its terminals to zero in order to keep the voltage time integral JVdt at a balance value. State 4: Gate turn-off device 21 turning on 20 Upon turning-on of the gate turn-off device 21, the out current Iout will commutate to the input terminal T1 again. The freewheel diode 22 will receive reverse bias and thus flows the reverse recovery current. This leads to that the current direction of the saturable core unit 5a becomes reversed, and the voltage is accepted across its terminals according to Fig. 25 1D. This results in an inductive current flowing in the saturable core unit 5a as long as the opposite saturation has not been reached. As a WO 2008/093429 PCT/JP2007/051848 14 consequence, such a current will have a nearly constant small dI/dt given by the equivalent inductance Lequ of the saturable core unit 5a in the non saturated region of the characteristic of Fig. 1D. In contrast to such an equivalent inductance, the clamp circuitry 3 5 directly feeds a change in the current to the switch arm 2 with a high dI/dt. This leads to that the charge carriers are extracted from the freewheel diode 22, which then gets reverse biased. Then, the clamp voltage reset circuitry 33 mainly will determine the reverse recovery load characteristic of the freewheel diode 22. Therefore, by the pure clamp 10 resistor 331 provided in the clamp circuitry 3, a resistive reverse recovery load condition is obtained at the freewheel diode 22. During this time period of the reverse recovery saturable core unit 5a has accumulated some voltage time integral fVdt, and builds up some current according to Fig. 1D. When the reverse recovery current 15 terminates, then saturable core unit 5a will reset the clamp capacitor 31, and go back to a near-center state of the saturation characteristic of Fig. 1D. 2-LEVEL INVERTER Referring to Fig. 1B, the forced commutated 2-level inverter further 20 includes the following in addition to the components of Fig. 1A: (a) a gate turn-off device 23, which is connected in parallel to the freewheel diode 22, (b) a freewheel diode 24, which is connected in parallel to the gate turn-off device 21, 25 (c) a saturable core unit 5b having a characteristic similar to that of the saturable core unit 5a, which is inserted between the input terminal WO 2008/093429 PCT/JP2007/051848 15 T1 and the anode leakage inductance 41, and (d) a controller 92 that generates and output gate control voltage signals to the gates of the gate turn-off devices 21 and 23, respectively, to alternatively turn off the gate turn-off devices 21 and 23. 5 In this case, a switch arm 2b including the two diodes 22 and 24 is provided in stead of the switch arm 2 of Fig. 1A. A part of the reverse recovery current of each of the freewheel diodes 22 and 24 originating from the DC-link capacitor 11 is controlled by at least one of the saturable core units 5a and 5b. As shown in Fig. 1B, the circuitry of the 2-level 10 inverter is made to be symmetrical, the same circuitry can accept a positive load current, which goes out to an external circuitry, and can accept a negative load current, which flows into an internal circuitry. The operation of the 2-level inverter is very similar to that as explained with the chopper circuitry of Fig. 1A for both directions of a load current except 15 for one difference, which is explained with respect to the positive load current in the following. When the gate turn-off device 21 is turned on, then its anode is not directly supplied from the DC-link capacitor 11 through the anode leakage inductance 41 in a manner similar to that of the chopper shown in Fig. 1A. 20 In stead of this, the saturable core unit 5b is connected on that line, and it is found in the center position of its characteristic of the saturable core unit 5b as shown in Fig. ID, since there was no current before. As a consequence, the gate turn-off device 21 will mainly conduct a current originating from clamp circuitry 3, until the saturable core unit 5b is 25 saturated to connect the gate turn-off device 21 to the DC-link capacitor 11.

WO 2008/093429 PCT/JP2007/051848 16 3-LEVEL INVERTER Referring to Fig. 1C, the forced commutated 3-level inverter includes a switch arm 2c in stead of the switch arm 2b of Fig. 1B, and further includes an input terminal T3, a saturable core unit 5c, a clamp circuitry 5 6, and an anode leakage inductance 42 in addition to those of Fig. 1B. Further, the forced commutated 3-level inverter includes a controller 93 for controlling gate turn-off devices 21, 23, 25, and 27, in stead of the controller 92 of Fig. 1B. In Fig. 1C, the DC-link capacitor 11 is connected between the input terminals T1 and T3, and the DC-link capacitor 12 is 10 connected between the input terminals T2 and T3. The input terminal T3 is connected through the saturable core unit 5a to the clamp circuitries 3 and 6, and the switch arm 2c. The input terminal T2 is connected through the saturable core unit 5c to the switch arm 2c. The clamp circuitry 6 includes a clamp capacitor 61, a clamp diode 62, and a clamp 15 voltage reset circuitry 63 including a resistor 631. The switch arm 2c includes not only the four gate turn-off diodes 21, 23, 25, and 27, but also six freewheel diodes 22, 24, 26, 28, 291, and 292 for use in a typical 3-level inverter, namely, which include the freewheel diode 22, the freewheel diode 24, the freewheel diode 26, the freewheel 20 diode 28, the zero point freewheel diode 291, and the zero point freewheel diode 292. Among these freewheel diodes 22, 24, 26, 28, 291 and 292, two freewheel diodes 22 and 28 do not receive any reverse recovery current in the inverter. The other four freewheel diodes 24, 26, 291 and 292 may receive a reverse recovery current from at least one of the DC 25 link capacitors 11 and 12. Such a reverse recovery current will flow on the P-line through the WO 2008/093429 PCT/JP2007/051848 17 input terminal T1 when the freewheel diode 24 receives a reverse recovery current, flow on the C-line through the input terminal T3 when the zero point freewheel diode 291 or zero point freewheel diode 292 receives a reverse recovery current, or flow on the N-line when the freewheel diode 5 26 receives a reverse recovery current. As a consequence, at least one of the saturable core units 5a, 5b and 5c is placed on each of these P-, C-, and N-lines. The 3-level inverter of Fig. 1C operates in a manner similar to that of the 2-level inverter of Fig. 1B. OTHER MULTI-LEVEL INVETERS 10 Figs. 1A, 1B, and 1C show the most commonly used forced commutated high power inverters, however, the present invention is not limited to these. The other multi-level inverter including the same saturable core units 5a, 5b and 5c may be provided. APPEARANCE OF DANGEROUS DIODE STRESS FOR 15 UNDERSTANDING CHARACTERISTIC AT THE LOWER LIMIT FOR SATURATION CURRENT Isat However, a dangerous reverse recovery stress may impact the freewheel diodes 24 and 26 and/or the zero point freewheel diodes 291 and 292, if the saturable core units 5a, 5b and/or 5c are not in the 20 correct saturation status prior to the turn-on of the gate turn-off device 21, 23, 25, and 27. Such incorrect magnetization status may originate from a current flowing in the saturable core units 5a, 5b and/or 5c as caused by the reset of the clamp capacitor 31 or 61. The incorrect saturation status also may result from displacement 25 current running to the clamp capacitor 31 having a capacitance C31 or the clamp capacitor 61 having a capacitance C61. Such a displacement WO 2008/093429 PCT/JP2007/051848 18 current originates from a change in the voltage across the DC-link capacitor 11 or 12. The maximum value of such a current is calculated by an equation of Idis = C31 x dVm or Idis = C 6 1 x dVm, where dVm denotes the maximum value of the absolute value of the rising rate of the voltage 5 across the DC-link capacitor 11 or the DC-link capacitor 12. Therefore, the rising rate dVm will satisfy a relation of -dVm dVDC/dt dVm, with dVDc/dt being the rising rate of the voltage across DC-link capacitor 11 or 12. Basically, there seems no means to avoid, that such displacement 10 current may influence the saturation status of the saturable core unit 5a, 5b or 5c. However, it is indispensable to make sure, that a core unit will not come close to an inappropriate saturation state. As a consequence, a self-resetting characteristic is required, which can return the saturation status to a well-defined, safe position under all circumstances. 15 Such a reset-characteristic is not found with a prior art core characteristic, which can provide only one stable saturation state at either extreme position. Instead, a linear region as shown in Fig. ID or at least a curved, the gradual region between the saturation extremes must be provided in order to define a reset level well between both the saturation 20 extremes. In addition, resetting of the clamp capacitor voltage and transfer of any displacement current have to be carried out in such a way, that a sufficient distance to the saturation is attained, when one of the gate turn off device 21, 23, 25 or 27 is turned on. Therefore, the saturation current 25 Isat needs to be selected at least so as to be larger than the maximum of all such displacement currents flowing in the saturable core unit 5a, 5b or 5c WO 2008/093429 PCT/JP2007/051848 19 as follows: Isat > Iais = C 31 x dVm or Isat > Idis = C 6 1 x dVm. Moreover, a design is clearly preferred, where the saturable core unit 5a, 5b or 5c will keep at least 75 % of its nominal isolation capability, when it is loaded with the worst case current of Iais = C3i x dVm or Iais = C6 1 5 x dVm. As a consequence, then the following equation is to be set: 'sat > 4 X Iais = 4 x C 3 1 x dVm, or Isat > 4 X Idis = 4 X C 6 1 x dVm. UNDERSTANDING UPPER LIMIT FOR SATURATION CURRENT Isat Basically, the conditions as explained above may be satisfied easily 10 by selecting a very high value for the saturation current Isat. However, the saturable core unit 5a, 5b or 5c will store the energy E under its non saturated status right in the same way, as a linear inductor does. If such a non-saturated status exhibits purely linear characteristics, then such energy E could be calculated by the following equation: 15 E = 1/2 x Lequ x I 2 , wherein Lequ denotes an equivalent inductance of the saturable core unit 5a, 5b or 5c, which is Lequ = V/(dI/dt) = JVdtsat /I under such linear conditions. When the saturation is reached, then the energy stored at such moment in time is trapped. Then such an amount Esat of energy 20 becomes Esat = 1/2 x Lequ x Isat 2 . It is released to the circuitry, when the core unit is later driven out of such a saturation status again. Since one main drawback of a prior art design is found in the large amount of stored energy, a low inverter loss will demand a small amount of stored energy. As a consequence, it is mandatory to set a saturation 25 current Isat to a small value. It needs to be set smaller than the maximum rated output current IRout to achieve the saturation status in any case as WO 2008/093429 PCT/JP2007/051848 20 follows: 0 < Isat < IRout. In order to achieve a low level of stored energy, furthermore a level below 20 % of the maximum rated output current is strongly preferable so as to satisfy the following inequality: 0 < 'sat < IRout/5. 5 CALCULATION EXAMPLES Finally, calculation examples based on practical values will be provided as follows: A high power inverter has a maximum rated output current IRout = 6000 A, a rated DC-link voltage VDc = 3500 V, and an average switching 10 frequency of 400 Hz. The DC-link capacitors 11 and 12 may be each designed to a typical value, allowing a voltage ripple of about ± 10 % at the nominal peak output current, which for the sake of safety, a margin is typically set to INoutpeak# IRout/ 1.5 = 4000 A. As a consequence, a rate of change of the DC-link voltage dVDc/dt (3500 IV] x 2 x 10 %)/ 1.25 [milli 15 second] = 560 [V/milli-secondl = dVm may appear. Such an inverter may typically require a value of the clamp capacitor 31 of C 3 1 = 20 pF. Then, 4 X C 31 x dVm = 4 x 20 [pF] x 560 [V/milli-second] = 44.8 [A] < Isat is to be set in the first preferred embodiment, with Isat < 6000 A/5 = 1200 A for the preferred upper limit. 20 SECOND PREFERRED EMBODIMENT Referring to Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 21, and 2J, further characteristics of the saturable core unit 5a, 5b and 5c which can be applied to the inverter of the first preferred embodiment are shown and explained, which are used to create a forced commutated high power 25 inverter according to the second preferred embodiment of the present invention.

WO 2008/093429 PCT/JP2007/051848 21 Fig. 2A is a graph showing an electrical characteristic of a voltage time integral fVdt to a current I of each of saturable core units 5a, 5b and 5c shown in Figs. 1A, 1B and 1C while defining a saturation voltage time integral J Vdtsat thereof according to a second preferred embodiment of the 5 present invention. Fig. 2B is a graph showing a relation between a reverse recovery charge Qr and a forward current I flowing in a typical high voltage high power silicon diode at an elevated junction temperature. In addition, Fig. 2C is a waveform chart showing (a) voltages Vsa and Vsb of the saturable voltage units 5a and 5b, (b) a normalized magnetic 10 flux F5a and F5b thereof, and (c) a voltage V 2 2 and a current 122 of a diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an output current Iout = 100 A. Fig. 2D is a waveform chart showing (a) the voltages V5a and Vsb of the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and F5b thereof, and (c) the voltage V 22 and 15 the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an output current Iout = 400 A. Fig. 2E is a waveform chart showing (a) the voltages V5a and V9b of the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and F5b thereof, and (c) the voltage V 22 and the current 122 of the diode 22 for use 20 in the 2-level high power inverter of Fig. 1B in the case of an output current lout = 1000 A. Fig. 2F is a waveform chart showing (a) the voltages V5a and V5b of the saturable voltage units 5a and 5b, (b) the normalized magnetic flux F5a and F5b thereof, and (c) the voltage V 22 and the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in 25 the case of an output current Iout = 3000 A. Fig. 2G is a waveform chart showing (a) the voltages Va and V5b of the saturable voltage units 5a and WO 2008/093429 PCT/JP2007/051848 22 5b, (b) the normalized magnetic flux F 5 a and Fsb thereof, and (c) the voltage V 22 and the current 122 of the diode 22 for use in the 2-level high power inverter of Fig. 1B in the case of an output current Iout = 6000 A. In particular, Figs. 2C to 2G show signals as observed during commutation 5 of the load current from freewheel diode 22 to the gate turn-off device 21 at various values of positive load current at the 2-level inverter of Fig. 1B having a maximum rated output current IRout = 6000 A and a saturation voltage time integral fVdtsat = 2.4 mVseconds, also with the junction temperature of the freewheel diode 22 set to its maximum permissible 10 value. Further, Fig. 2H is a graph showing an estimated relation of an anode voltage to an anode current of the diode 22 for each turn-off with a parameter of output current lout for the conditions shown in Figs. 2C to 2G. Fig. 21 is a graph showing an estimated relation of a reverse recovery 15 power to an anode voltage of the diode 22 with a parameter of output current lout. Fig. 2J is a graph showing an estimated relation of a stress reverse recovery power to an output current Iout of the diode 22 for various circuitry configurations and respective settings of the saturation voltage time integral JVdtsat , in particular, Fig. 2J shows the highest value of 20 reverse recovery power at a reverse voltage of 3.5 kV or above, hereafter named "stress reverse recovery power", as a function of inverter output current Iout, as observed under various inverter circuitry conditions: (1) Curve 101 shows a stress reverse recovery power, using a prior art circuitry with the linear anode reactor 41 having an inductance L 41 of 25 7 pH; (2) Curve 102 shows a stress reverse recovery power in the case of a WO 2008/093429 PCT/JP2007/051848 23 saturation voltage time integral JVdtsat = 0.6 mVseconds, and an inductance L4 1 = 1 pH; (3) Curve 103 shows a stress reverse recovery power in the case of a saturation voltage time integral fVdtsat = 1.2 mVseconds, and an 5 inductance L 4 1 = 1 pH; (4) Curve 104 shows a stress reverse recovery power in the case of a saturation voltage time integral JVdtsat = 2.4 mVseconds, and an inductance L41 = 1 pH; (5) Curve 105 shows a stress reverse recovery power in the case of a 10 saturation voltage time integral f Vdtsat = 3.6 mVseconds, and an inductance L 41 = 1 pH; (6) Curve 106 shows a stress reverse recovery power in the case of a saturation voltage time integral fVdtsat = 4.8 mVseconds, and an inductance L41 = 1 pH; and 15 (7) Curve 107 shows an anode reactor adapted stress reverse recovery power capability. In a prior art chopper circuitry without the saturable core unit 5a of Fig. 1A, values for the curve 107 are derived experimentally using an adapted linear anode reactor for every current setting, which loads the diode to full capability at such anode current 20 setting. Fig. 2A shows a typical hysteresis loop as observed with a saturable core unit 5a of the first preferred embodiment. Then, the saturation voltage time integral JVdtsat is defined by the value at the saturation, which is characterized by a low inductance state of the core unit. 25 Such a characteristic showing a nearly constant slope in the non saturated state and another, very small slope in the saturated state may WO 2008/093429 PCT/JP2007/051848 24 be obtained with a single core or with a set of cores having all the same characteristics. However, a core unit having a gradient change of inductance may be also applied. Such a core unit may be obtained by using a series connection of core units having different characteristics or 5 by appropriate core material. In addition, in such a case, the saturation integral is defined as the highest achievable value of JVdt at practical conditions. Fig. 2B shows the reverse recovery charge as a function of forward current for a typical high voltage silicon diode. The relation is strongly 10 non-linear. At a low current, then there is a lot of charge per one Ampere of the forward current flowing in the diode. Figs. 2C to 2G show results as obtained with a diode used in the 2 level inverter of the second preferred embodiment at various inverter output currents lout. Fig. 2C shows a result at an output current lout = 15 100 A, Fig. 2D shows a result at an output current Iout = 400 A, Fig. 2E shows a result at an output current Iout = 1000 A, Fig. 2F shows a result at an output current lout = 3000 A, and Fig. 2G shows a result at an output current lout = IRout = 6000 A. In these cases, the top graph of each of Figs. 2C to 2G shows a voltage V5a across the saturable core unit 5a, 20 and a voltage V5b across the saturable core unit 5b. The middle graph of each of Figs. 2C to 2G shows a magnetic flux F5a in a saturation state of the saturable core unit 5a, and a magnetic flux F5b in a saturation state of the saturable core unit 5b. The bottom graph of each of Figs. 2C to 2G shows an anode current 122 flowing in the freewheel diode 22, and an 25 anode voltage V 2 2 across the freewheel diode 22. Each of the saturable core units 5a and 5b has a saturation voltage time integral JVdtsat = 2.4 WO 2008/093429 PCT/JP2007/051848 25 mVseconds, and a saturation current Isat = 160 A, consequently, having an equivalent inductance Lequ = 15 pH. Referring to 2C, both the saturable core units 5a and 5b start with zero voltage at a time t = 334 seconds. Then, the saturable core unit 5b 5 has zero saturation level, while the saturable core unit 5a shows a saturation level of JVdt = 0.62 x jVdtsat. At that moment in the time t = 334 pseconds, the freewheel diode 22 is forward biased so that the anode current 122 = 100 A, and the anode voltage V 22 = 1.5 V. At the turn-on of the gate turn-off device 21 at a time t = 335 seconds, both the saturable 10 core units 5a and 5b receive the voltages, respectively, and this leads to both changing the saturation status, and the freewheel diode 22 receives a negative anode current 122. Then, such an anode current 122 mainly originates from the clamp circuitry 3, and it increases fast to reach nearly 122= IkA. However, such a high anode current is only applied to the 15 freewheel diode 22 in a state of relatively small anode voltage, and after a time t = 336 seconds, the anode current 122 can already decrease, while the anode voltage V 22 across the freewheel diode 22 slowly approaches the value of DC-link capacitor 11 such as VDC = 3650 V. During all such a time interval, both the saturable core units 5a and 5b stay in the non 20 saturated state, providing a full inductance of 2 x Lequ = 30 pH to isolate or electrically insulate the switch arm 2b of Fig. 1B from the DC-link capacitor 11. Referring to Fig. 2D with an output current lout = 400 A, the saturable core unit 5a already starts at a saturation voltage level of fVdt 25 = 1 x JVdtsat so that the saturable core unit 5a has been completely saturated. Then, the saturable core unit 5b changes the saturation state WO 2008/093429 PCT/JP2007/051848 26 first, running to a complete saturation. The saturable core unit 5a starts later, then completely running through the non-saturated region and reaching the opposite saturation at a time t = 941 pseconds. In this way, the freewheel diode 22 does not receive any current from DC-link 5 capacitor 11 under isolation by the saturable core unit 5a, until the anode voltage V 2 2 has reached the DC level VDC = 3650 V, and the reverse recovery current has come to zero. Therefore, an inductance of 1 x Lequ = 15 pH is provided to isolate the switch arm 2B from the DC-link capacitor 11, when the diode runs to a high voltage. 10 Referring to Fig. 2E with an output current Lout = 1000 A, the saturable core unit 5a again starts at a complete saturation. The saturable core units 5a and 5b become active one after another. The saturable core unit 5a now reaches a complete saturation already at a time t = 1540 pseconds, that is about 4 pseconds before the end of the 15 diode's tail current. As a consequence, the DC-link capacitor 11 is directly connected to the freewheel diode 22 at that time, and then, the anode current 122 thereof ramps up a little. Referring to 2F with an output current Iout = 3000 A, both the saturable core units 5a and 5b act even faster, and the reverse recovery 20 current flows for a longer time. As a consequence, the saturable core unit 5a has already reached the saturation state about 7.5 pseconds before the end of the diode's tail current, then significantly ramping up the anode current 122. Referring to Fig. 2G with an output current Iout = 6000 A, this effect 25 is even more pronounced. However, even then the anode voltage V 2 2 has reached V 2 2 = 2 kV, when the freewheel diode 22 is connected to the DC- WO 2008/093429 PCT/JP2007/051848 27 link capacitor 11. Despite a small loop inductance provided by the anode leakage inductance 41 such as L = 1 pH, a rising rate d12 2 /dt of the anode current 122 is rather small, and the anode current 122 stays so that 122 < 2000 A. 5 Fig. 2H estimates corresponding reverse recovery operating areas, plotting the anode voltage V 2 2 as a function of the anode current 122 for every reverse recovery of the freewheel diode 22. This estimation shows a small anode current at a high anode voltage at a reverse recovery from low and medium forward currents Iout = 100 A and 400 A. 10 Fig. 21 shows the next estimation step. It shows a product of the reverse recovery voltage and the reverse recovery current, namely, the reverse recovery power, as a function of the reverse recovery voltage or the anode voltage V 22 . In the cases of an output current Iout = 100 A and Lout = 400 A, the value of the reverse recovery power is small at an anode voltage 15 V 22 = 3.5 kV. The circuitry of the 2-level inverter according to the second preferred embodiment then does perfectly protect the freewheel diode 22 under such conditions. Fig. 2J shows another estimation step, namely, a comparison by plotting the stress reverse recovery power as a function of the inverter 20 output current Iout for various circuitry configurations and settings of the saturation voltage time integral JVdtsat . In this case, the diode reverse recovery stress under the maximum specified load conditions of a prior art is represented by a dashed curve 101 of Fig. 2J. From the graph of Fig. 2J, it is understood that, with respect to the curve 101, a small setting of the 25 saturation voltage time integral J Vdtsat as compared with the saturation voltage time integral JVdtsat = 0.6 mVseconds of the curve 102 can WO 2008/093429 PCT/JP2007/051848 28 already reduce the diode stress in the case of a smaller anode current 122. However, in the case of a higher anode current 122, the diode stress is higher than that of the curve 101, with a crossover at an anode current 122 = 400 A. 5 A setting to the saturation voltage time integral JVdtsat = 1.2 mVseconds of the curve 103 of Fig. 2J will reduce the diode stress below a level as observed with a prior art circuitry of the curve 101 at all the currents smaller than 2800 A. A setting to the saturation voltage time integral fVdtsat = 2.4 10 mVseconds of the curve 104 will result in a reduced stress level throughout the complete operation range. A setting to the saturation voltage time integral IVdtsat = 3.6 mVseconds of the curve 105 or JVdtsat = 4.8 mVseconds of the curve 106 will result in a very low stress level throughout the complete operation 15 range. Consequently, a target value for the saturation voltage time integral f Vdtsat is derived from Fig. 2J. With the curve 107, the anode reactor adapted stress reverse recovery capability Prriar (I) is introduced. In the case of a prior art chopper circuitry of Fig. 1A without any saturable core 20 unit 5a, the curve 107 plots the maximum reverse recovery stress capability of a high voltage diode as derived under variation of the anode reactor 41. Then, for every current value of the curve 107, a new value is set to the anode reactor 41 in such a manner that the freewheel diode 22 is loaded to its limit at its reverse recovery from such a current. 25 The second preferred embodiment of the present invention is able to adapt well to these maximum permissible stress values as follows. When WO 2008/093429 PCT/JP2007/051848 29 selecting the saturation voltage time integral JVdtsat = 0.6 mVseconds, then the stress reverse recovery power Prr (I) of the curve 102 has been already smaller than the anode reactor adapted stress reverse recovery power capability of such a diode represented by the curve 107 in the 5 complete inverter output current lout in a range of 0 I lout : IRout. According to the second preferred embodiment of the present invention, the value of the saturation voltage time integral JVdtsat is further selected such that PR, (I) ; 1/2 x Prriar (I) at at least one output current value Iout in a range of 0 5 Iout IRout. In Fig. 2J, the curve 106 is 10 close to such a limit that: in the case of lout = lRout = 6000 A, it is Prriar (I) of the curve 107 = 7.9 MVA, whereas Pr (I) of the curve 106 = 4.1 MVA. Under such a condition as the saturation voltage time integral J Vdtsat = 4.8 mVseconds, diode recovery is extremely smooth, but the saturable core units 5a and 5b have become considerably large, then transferring a 15 high amount of energy to the clamp circuitry 3 and the clamp circuitry 6, respectively. In this way, the inverter according to the second preferred embodiment of the present invention adapts in a preferred way to the characteristics of typical high power silicon diodes. Very small values of 20 the anode leakage inductance 41 and 42, and very small core units 5a and 5b are applied, resulting in low manufacturing cost and low inverter loss during operation. THIRD PREFERRED EMBODIMENT Fig. 3A is a block diagram showing the saturable core unit 5a 25 according to the third preferred embodiment of the present invention, and Fig. 3B is a perspective view showing an appearance of the saturable core WO 2008/093429 PCT/JP2007/051848 30 unit 5a of Fig. 3A. Referring to Fig. 3, the saturable core unit 5a which can be applied to the first or second preferred embodiment is shown to provide a forced commutated high power inverter according to the third preferred 5 embodiment. In the present preferred embodiment, the saturable core unit 5a includes a saturable inductor 51, where the saturable inductor 51 includes at least one gap 5g. Another material of the gap 5g may be introduced to the magnetic loop of the saturable core unit 5a. In most cases, such a material of the 10 gap 5g is completely non-magnetic, depending on the mechanical design of the core, and the material of the gap 5g may be some type of plastic or just air. Then, the magnetic flux cD have to run through the core material and through the gap material. In the magnetic core material, the 15 magnetic flux density B = CD/A, where A is an area of the cross-section penetrated by the magnetic flux CD, then this gives a magnetic field Hfe = B/ppo, whereas the magnetic field in the non-magnetic material is Hair = B/po. Then, the ring-integral JHds along a closed path through the core and gap 5g of the saturable core unit 5a is derived to determine the 20 current penetrating through the core. If the size of the gap 5g is large enough to dominate the integral f Hds , then the inductance L of the turned coil of the core thereof is approximately L (po n 2 A) /lair, where li denotes the thickness of the gap 5g as filled with a non-magnetic material, and "n" is the number of turns. 25 The gap 5g is often applied to magnetic cores of inductors or transformers, when a large DC-offset current is present on such WO 2008/093429 PCT/JP2007/051848 31 components. The gap 5g is often called "air gap", and the B-H characteristic is changed to present or make an enlarged region having nearly linear B-H-relation. Then it is the linear region, which is to be extended by the gap 5g and which is used, and the saturation of the core 5 material is totally undesired. In the third preferred embodiment, however, the gap 5g is incorporated to establish a characteristic such as shown in Fig. 1D. Then the gap 5g sets the equivalent inductance Lequ of the core as shown above, and this leads to that it sets the saturation current Isat = fVdtsat /Lequ. 10 Consequently, by the third preferred embodiment of the present invention, a method is presented to realize the saturable core units 5a, 5b and 5c each having a linear characteristic in a very efficient way. FOURTH PREFERRED EMBODIMENT Fig. 4 is a circuitry diagram showing a configuration of a forced 15 commutated high power inverter according to a fourth preferred embodiment of the present invention. In the present preferred embodiment, the saturable core units 5a, 5b and 5c are each made by a parallel connection circuitry of a saturable inductor 51, 52 or 53 and a linear reactor inductor 71, 72 or 73, 20 respectively, where the saturable inductors 51, 52 and 53 are characterized by a saturation voltage time integral fVdtsat, and the linear reactors 71, 72 and 73 are characterized by a value of an equivalent inductance Lequ = JVdtsat /Isat. It is to be noted that a controller 94 operates in a manner similar to that of the controller 93. 25 In the inverter according to the fourth preferred embodiment, the most preferred characteristics of each of the saturable core units 5a, 5b WO 2008/093429 PCT/JP2007/051848 32 and 5c are achieved by a parallel circuitry of two separate devices. In this case, each device is dedicated to one of the preferred characteristics, the saturation voltage time integral j Vdtsat and the equivalent inductance Lequ of the linear region. In this way, stable and low loss saturable core 5 units 5a, 5b and 5c are realized. In other words, the saturable inductors 51, 52 and 53 are selected for the lowest hysteresis loss, and the linear inductors 71, 72 and 73 are designed to the saturation current Isat only. The Lowest hysteresis loss in general is achieved by a saturable core having a steep and narrow B-H-characteristic, which then results in a 10 very small saturation current of the saturable core. In contrast to the linear anode reactor applied in a prior art inverter, the linear inductor is designed to the saturation current 'sat only. As a consequence, a low hysteresis loss is paired with a low conduction to result in a high inverter efficiency. 15 FIFTH PREFERRED EMBODIMENT In Fig. 5A to 5E, a forced commutated high power inverter according to the fifth preferred embodiment is shown. Fig. 5A is a circuitry diagram showing a configuration of the saturable core unit 5a for use in the forced commutated high power inverter according to the fifth preferred 20 embodiment of the present invention. In the present preferred embodiment, as shown in Fig. 5A, resistors 511 and 711 are incorporated in the path of saturable inductor 51 and in the path of the linear inductor 71, respectively, and they are balanced according to the following equation: 25 (IDC5a X R511)/R 71 1 ! sat/2, and preferably, (IDC5a x R 5 1 1 )/R711 Isat/5.

WO 2008/093429 PCT/JP2007/051848 33 In the experiment of Fig. 5A, the following parameters are used: (a) a voltage time integral Vdt = 2.4 mVseconds for the saturable inductor 51; (b) a resistance of the resistor 511, R51 = 10 pQ; 5 (c) an inductance of the linear inductor 71, L 71 = Lequ = 25 pH; (d) a saturation output current Isat = 96 A; (e) a DC current flowing in the saturable core unit Sa, IDcsa -1000 A; and (f) an AC current flowing in the saturable core unit 5a, IAC5a 3000 10 Apeak. The impact of the resistors 511 and 711 balancing on the performance of the inverter will be explained with reference to Figs. SB to 5E, which show typical signals of the saturable core unit 5a under a load with a DC-offset IDCsa = 1000 A at a time ti. Thereafter, the load is 15 terminated to check the core reset. In Figs. 5B to 5E, the top graph shows the current I5a flowing in the saturable core unit 5a, and the bottom graph shows a current 171 flowing in the linear inductor 71, and also shows a normalized magnetic flux or normalized magnetization of the saturable inductor 51. 20 Fig. 5B is a waveform chart of a first part in an unbalanced case showing (a) a current Isa of the saturable core unit 5a, and (b) a current 171 of an inductance 71 of Fig. 5A and a normalized magnetic flux F5 1 of a saturable inductor 51 of Fig. 5A, and Fig. 5C is a waveform chart of a second part in the unbalanced case showing (a) the current I5a of the 25 saturable core unit 5a, and (b) the current In of the inductance 71 of Fig. 5A and the normalized magnetic flux Fqi of the saturable inductor 51 of WO 2008/093429 PCT/JP2007/051848 34 Fig. SA. Figs. 5B and 5C show an unbalanced case with R511 = R7u = 10 pQ. At the reset check after a time ti = 4 milli-seconds of Fig. 5B, the core unit 5a does well as follows. Then the core unit 5a returns to a condition having a saturation status of JVdt 0 x JVdtsat . At the reset check 5 after ti = 199 milli-seconds of Fig. 5C, however, the core unit 5a fails resetting as follows. Then the core unit 5a returns to a condition of jVdt -1 x fVdtsat Fig. 5D is a waveform chart of a first part in a preferred case showing (a) the current I5a of the saturable core unit 5a, and (b) the 10 current 171 of the inductance 71 of Fig. 5A and the normalized magnetic flux F 5 i of the saturable inductor 51 of Fig. 5A, and Fig. 5E is a waveform chart of a second part in the preferred case showing (a) the current Isa of the saturable core unit 5a, and (b) the current 171 of the inductance 71 of Fig. 5A and the normalized magnetic flux F 5 of the saturable inductor 51 15 of Fig. 5A. Figs. 5D and 5E show a preferred case with R 511 = 10 pQ, and R7u = 1 mQ. At the reset check after a time ti = 4 milli-seconds of Fig. 5D, the core unit 5a does well as follows. Then the core unit 5a returns to a condition of JVdt 4 0 x fVdtsat. At the reset check after a time ti = 199 milli-seconds of Fig. 5E, the core unit 5a is still reset well as follows. Then 20 the core unit 5a returns to a condition of JVdt 0.07 x JVdtsat Finally, it is mentioned that a timing relation should be observed. As is also understood from Fig. 5D, the current flowing in the linear inductor 71 and the inductor resistance 711 is set by the voltage time integral fed to them during each zero crossing transition of the current of 25 the saturable core unit 5a. Then, the current flowing in the linear inductor 71 is held to be constant, since the voltage across the saturable WO 2008/093429 PCT/JP2007/051848 35 core unit 5a becomes small. The time constant of the RL circuitry of the components 71 and 711 must be then large enough to hold the following current: T71-711 > 2 x tH, and 71-711 > 2 X tL, 5 where tH and tL denote time durations of the positive and negative currents on the saturable core unit 5a, respectively. Further, the time constant is determined by the values of the resistance Ryu and the inductance L 7 as follows: T7i-7u = L 7 /R71u. 10 Then, the upper limit is concluded as follows: R711 < 1/2 x L 7 1 /tH, and R7 1 1 < 1/2 x L71/tL. Moreover, even significantly higher current conservation is preferred. Therefore, the following relations are more preferred: R71 < 1/4 x L71/tH, and R 71 i < 1/4 x L71/tL. 15 The inverter according to the fifth preferred embodiment can surely make the correct reset of the saturable core unit 5a. SIXTH PREFERRED EMBODIMENT Fig. 6A is a circuitry diagram showing a configuration of a forced commutated high power inverter according to a sixth preferred 20 embodiment of the present invention. In particular, the present preferred embodiment is directed to the reverse recovery of the freewheel diode 22 and the freewheel diode 24 shown in Fig. 6A, but can be applied equally well to the other configurations such as a chopper circuitry, a 3-level inverter or the like. It is to be noted that a controller 96 operates in a 25 manner similar to that of the controller 92. High voltage freewheel diodes 22 and 24 typically tend to become WO 2008/093429 PCT/JP2007/051848 36 "snappy", if they are designed for high speed and low reverse recovery loss. The snappiness shows at the end of the reverse recovery process. Then quite suddenly, all the charge carriers have been extracted, and then, the reverse recovery current falls to the zero current. As a consequence, large 5 over-voltage spikes and oscillations are observed therein. The snappy behavior strongly depends on the forward current flowing in each of the diodes 22 and 24. With a high forward current by a high load, each of the diodes 22 and 24 may typically behave relatively soft, but with a small forward current, it is so snappy, that it may be 10 already destroyed at a relatively small rising rate dI/dt. With a traditional circuitry of a prior art which is constituted by the chopper circuitry of Fig. 1A without the saturable core unit 5a, a reverse recovery condition of each of the diodes 22 and 24 is fixed to the same rising rate dI/dt in the case of a small and high forward current. In the 15 case of a small forward current, then this leads to a comparatively large reverse recovery current. Then, the maximum of reverse recovery current and the maximum of reverse recovery voltage appear at the same moment in the time. The above timing condition is characteristic for pure inductive load, and namely, it is most demanding to the diodes 22 and 24. 20 In contrast to the traditional chopper circuitry, the forced commutated high power inverter according to the second preferred embodiment of the present invention can cope with the difficult situation of the reverse recovery in the case of a small forward current much better as already shown in Fig. 2J. Further improvement is achieved by the 25 sixth preferred embodiment of the present invention. Fig. 6B is a waveform chart showing a voltage V5a of the saturable WO 2008/093429 PCT/JP2007/051848 37 core unit 5a of Fig. 6A, and a voltage V 22 and a current 122 of a freewheel diode 22 of Fig. 6A when a clamp circuitry 3 includes a clamp resistor 331 with a typical clamp resistor's leakage inductance 331a of 1.5 pH. The output current lout is set to Iout = 100 A. 5 The forced commutated high power inverter according to the sixth preferred embodiment is particularly directed to such difficult situation of reverse recovery in the case of a small forward current. In the sixth preferred embodiment further including a clamp voltage reset circuitry 33 which is comprised of a parallel connection circuitry of the following: 10 (a) a serial connection circuitry including a clamp resistor 331, and a clamp resistor's leakage inductance (or equivalent inductance) 331a; and (b) a serial connection circuitry of a low impedance RC network including a pulse limiting resistor 333, a pulse capacitor 334, and a 15 leakage inductance 334a. The above RC network is designed to contribute most to the total current of the clamp voltage reset circuitry 33 at the very beginning of receiving a voltage change. This leads to that the RC network will enhance the diode's reverse recovery current right at the beginning, and 20 later, it will add a damping to the clamp resistor's leakage inductance 331a. Fig. 6C is a waveform chart showing the voltage V 5 a of the saturable core unit 5a of Fig. 6A, and the voltage V 2 2 and the current 122 of the freewheel diode 22 of Fig. 6A when enhancing the diode's reverse recovery 25 current right in the beginning, and later adding a damping to the clamp resistor's leakage inductance 331a. As shown in Fig. 6C, the reverse WO 2008/093429 PCT/JP2007/051848 38 recovery of the freewheel diode 22 (or 24) has become extremely soft, and the diode 22 (or 24) is extremely well supported during the snap-off. SEVENTH PREFERRED EMBODIMENT Fig. 7A is a circuitry diagram showing a configuration of a forced 5 commutated high power inverter according to a seventh preferred embodiment of the present invention. The present preferred embodiment is directed to loss reduction. It is to be noted that a controller 97 operates in a manner similar to that of the controller 92. Fig. 7B is a waveform chart in the case without any delay core 336, 10 showing a voltage V5a of the saturable core unit 5a, a voltage V5b of the saturable core unit 5b, a voltage V 22 and a current 122 of the freewheel diode 22, and a current 133 of a clamp voltage reset circuitry 33. In this case, an output current lout is set to lout = 3000 A. It is understood from Fig. 7B, that at a high load current, a 15 relatively large current flows in the clamp voltage reset circuitry 33 for a relatively long time interval (ti - t 2 ) without any influence to the reverse recovery of the respective freewheel diodes 22 and 24. The time interval (ti - t 2 ) originates from the transition of saturable core unit 5b, which allows the gate turn-off device 21 to feed a current from the clamp 20 circuitry 3. The above current flow causes power dissipation in the clamp voltage reset circuitry 33. According to the seventh preferred embodiment, a delay core 336 is further inserted to the line of clamp resistor 331 and the clamp resistor's leakage inductance 331a. The above delay core 336 may be just another 25 saturable core. However, the effective current flowing in the delay core 336 is considerably smaller than the current flowing in each of the main WO 2008/093429 PCT/JP2007/051848 39 saturable core units 5a, 5b and 5c. Therefore, the delay core 336 may be designed considerably to be smaller than that of each of the saturable core units 5a, 5b and 5c. Fig. 7C is a waveform chart in the case with the delay core 336, 5 showing the voltage V5a of the saturable core unit 5a, the voltage V5b of the saturable core unit 5b, the voltage V 22 and the current 122 of the freewheel diode 22, and the current 133 of the clamp voltage reset circuitry 33. As is understood from Fig. 7C, the delay core 336 delays the current 133 flowing in the clamp resistor 331. As a consequence, loss reduction is achieved in 10 particular at a high operating current. INDUSTRIAL APPLICABILITY As mentioned above in details, according to the above-mentioned forced commutated high power inverter apparatus, since a saturable core unit is used in the forced commutated inverter apparatus, which has 15 incorporated a well-defined reset state and force, a well-defined operation can be performed under almost all conditions in a real application. As a consequence, reliable control of diode reverse recovery current can be performed.

Claims (14)

1. A forced commutated high power inverter apparatus having a maximum rated output current IRout, comprising: 5 at least one DC-link capacitor having a voltage ripple characterized by a maximum value dVm of an absolute value of a rising rate dVDC/dt, which satisfies a relation of -dVm5 dVDC/dt 5 dVm; at least one anode leakage inductance connected in series with the DC-link capacitor; 10 at least one switch arm including a series connection circuitry of at least one gate turn-off device and at least one freewheel diode; at least one clamp circuitry including at least one clamp capacitor, at least one clamp diode, and at least one clamp voltage reset circuitry which includes at least one resistor; and is at least one saturable core unit, wherein said at least one saturable core unit has one of a linear saturation characteristic and a gradual saturation characteristic, each having a saturation current 'sat, and wherein the saturation current Isat is set to be larger than a displacement current 20 created by a rising rate of dVm, with a capacitance C 3 1 of said at least one clamp capacitor, so as to satisfy a relation of the following equation: IRout > Isat > C31 X dVM.

2. The forced commutated high power inverter apparatus according to claim 1, 25 wherein the saturation current Isat is set to satisfy a relation of the following equation: 41 'Rout > Isat > 4 X C 3 1 X dVm.

3. The forced commutated high power inverter apparatus according to claim I or 2, wherein the saturation current Isat is set to satisfy a relation of the following equation: 5 IRout /5 > Isat > C 3 1 x dVm.

4. The forced commutated high power inverter apparatus according to claim I or 2, wherein the saturation current Isg is set to satisfy a relation of the following equation: IRout /5 > Isat > 4 X C 31 x dVm. i0

5. The forced commutated high power inverter according to any one of claims I to 4, wherein said at least one freewheel diode has an anode reactor adapted stress reverse recovery power capability Prriar (I) which is determined using adapted linear anode is reactors, wherein said at least one saturable core unit has a saturation voltage time integral JVdt,. , wherein said forced commutated high power inverter creates a stress reverse recovery power Pr(I) upon said at least one freewheel diode, 20 wherein the saturation voltage time integral fVdt, is selected so that Pr(I) 5 Peiar(I) for said diodes under reverse recovery stress as caused within an inverter output current in a range of 0 < 'out 5 IRout, and wherein the saturation voltage time integral fVdt, is selected so that P 1 (I) > 1/2 x Priar(I) for at least one diode under reverse recovery stress among said diodes for at 42 least one current level 1 It as caused within an inverter output current in a range of 0 < Iout < 'Rout.

6. The forced commutated high power inverter according to any one of claims I to 5 5, wherein said at least one saturable core unit comprises at least one saturable inductor, having at least one gap filled with non-magnetic material so that said at least one saturable core unit has the saturation current Isat. 10

7. The forced commutated high power inverter according to any one of claims I to 5, wherein said at least one saturable core unit comprises at least one saturable inductor, and at least one linear inductor, which is connected parallel to said at least one saturable inductor, is wherein said at least one saturable inductor is characterized by the saturation voltage time integral fVdtst of said at least one saturable core unit, and wherein said at least one linear inductor has an inductance L 7 1 = Lequ = Vdt. / Isat derived from the saturation voltage time integral Vdts and the saturation current Isat of said at least one saturable core unit. 20

8. The forced commutated high power inverter according to claim 7, wherein said at least one saturable core unit flows a maximum DC current component IDC5a, 43 wherein said at least one saturable core unit further comprises at least one saturable core bus resistance R 511 , and at least one inductor resistance R 71 , and wherein said at least one saturable core bus resistance R 51 , and said at least one inductor resistance R 7 11 are set to satisfy the following equations with a time duration tH 5 of positive current and a time duration tL of negative current flowing in said saturable core unit: (IDC5a x R 5 , 1 ) / R 71 < 1/2 x Isat, and R 711 < 1/2 x L71/tH and R7 1 i < 1/2 x L71/tL. io

9. The forced commutated high power inverter according to claim 8, wherein said at least one saturable core bus resistance R5 1 , and said at least one inductor resistance R 71 are set to satisfy the following equations: (DC5a x R, 5 1 ) / R 71 5 1/2 X Isat, and R 711 < 1/4 x L71/tH and R 7 11 < 1/4 x L71/tL. 15

10. The forced commutated high power inverter according to claim 8, wherein said at least one saturable core bus resistance R 51 1 and said at least one inductor resistance R 7 11 are set to satisfy the following equations: (IDC5a x R5 1 1) / R7 1 5 1/5 X Isat, and 20 Ry1 < 1/2 x L71/tH and R71i < 1/2 x L71/tL.

11. The forced commutated high power inverter according to claim 8, wherein said at least one saturable core bus resistance R5 11 and said at least one inductor resistance R7H are set to satisfy the following equations: 25 (IDC5a x R5, 1 ) / R 711 1/5 X Isat, and 44 R71 < 1/4 x L7I/tH and R711 < 1/4 x L71/tL.

12. The forced commutated high power inverter according to any one of claims 1 to 11, 5 wherein said at least one clamp voltage reset circuitry further comprises at least one clamp resistor, at least one pulse capacitor, and at least one pulse limiting resistor.

13. The forced commutated high power inverter according to claim 12, wherein said at least one clamp voltage reset circuitry further comprises at least one delay core. 10

14. A forced commutated high power inverter apparatus having a maximum rated output current IRout, the forced commutated high power inverter apparatus being substantially as hereinbefore described with reference to any one of the embodiments as that embodiment is shown in the accompanying drawings. i5 DATED this Twenty fifth Day of August, 2010 Toshiba Mitsubishi-Electric Industrial Systems Corporation Patent Attorneys for the Applicant SPRUSON & FERGUSON 20