RU2400916C1 - Design of inverter with forced switching - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device is suggested, which represents inverter of high capacity with forced switching, having maximum rated output current I_Rout. It comprises DC-coupling capacitor, anode stray inductance, switch arm, circuit of level fixation and unit with saturated core. Besides DC-coupling capacitor has voltage pulsation characterised by maximum value dV_m of absolute value of growth speed dV_DC/dt, and anode stray inductance is connected serially to DC-coupling capacitor. Switch arm comprises circuit of serial connection of locked valve device, and reverse diode, and circuit of level fixation includes fixing capacitor, fixing diode and circuit of fixation level voltage collapse, including resistor. Unit with saturated core has one of linear saturation characteristic and smooth saturation characteristic, every of which has saturation current, equal to I_sat and established so that ratio I_Rout>I_sat>C₃₁×dV_m, where C₃₁ is capacitance of fixing capacitor.

EFFECT: elimination of transistor overloads in reverse recovery.

13 cl, 28 dwg

Description

The present invention relates to a forced-switching inverter device, in particular to a forced-switching inverter device for a high power voltage source, which comprises lockable valve devices, such as, for example, gate-switched valves (GCTs), insulated gate transistors, and Extended Injection (IEGTs) or Insulated Gate Bipolar Transistors (IGBTs), Reverse Diodes, and Level Lock Circuit.

BACKGROUND OF THE INVENTION

Each of the forced-switching inverter devices for a high-power voltage source contains lockable gate devices, reverse diodes, a level locking circuit, and a direct current storage unit, such as a capacitor bank. Depending on the application, various types of circuit configuration are used, for example, a chopper configuration, a two-level configuration, a three-level configuration, and a multi-level configuration.

In the open state, each of the high-voltage reverse diodes used in practice, having a blocking capacity of, for example, 4.5 kV or 6 kV, accumulates a significant amount of charge carriers. Then, these charge carriers must be removed by reverse current before a closed state is obtained.

Due to the presence of such a reverse recovery current, these diodes will have a relatively low impedance for a short time after initiating the reversal condition. Therefore, in order to avoid the occurrence of any excess current, it is necessary to apply some kind of current control. Essentially, the following two types of reverse recovery current control using passive elements have been proposed:

(a) current control using linear anode electric reactors and

(b) current control with saturable cores.

The following is a description of the control current reverse recovery linear anode electric reactor of the prior art, which is disclosed in the following patent documents:

(a) in European Patent Laid-Open Publication No. EP-0776083-A2 (which is hereinafter referred to as the first patent document);

(b) in US patent No. 5768114, which relates to the family of the first patent document; and

(c) in Japanese Patent No. JP-3749580-B2, which relates to another family of the first patent document.

In the first patent document, a damper-free reverse recovery control by a linear anode electric reactor is disclosed, and a circuit breaker circuit for a forced-switching high-power voltage source using a linear anode electric reactor of the prior art is disclosed. The chopper circuit includes a DC coupling capacitor, which is supplied via input lines, a switch arm containing a lockable gate device, and a return diode, an anode electric reactor, and a level locking circuit containing a fixing diode.

In the experimental example of the chopper circuit, after the current flowing through the reverse diode to zero, the reverse diode then provides reverse recovery, namely, the charge carriers in the reverse diode still maintain high conductivity, while the direction of the anode current is reversed. As a result, the voltage at the reverse diode remains close to zero for a certain period of time. After that, the voltage at the reverse diode may decrease, approaching the value of the DC coupling voltage. Namely, due to the inductance of the anode electric reactor, the anode current flowing in the reverse diode continues to increase, and then the same current can be switched into a level fixing circuit. In this case, the voltage at the reverse diode remains close to the DC voltage across the coupling capacitor, and the anode current flowing through the reverse diode can be reduced.

In typical characteristics of the dependence of the anode voltage on the anode current for the reverse diode used above, for each forward current flowing through it, the reverse voltage approaches the highest value when the anode current also approaches the highest value. In this case, a high apparent power of reverse recovery is created in the diode with an increased anode voltage, causing, therefore, a high level of harmful effects of reverse recovery. In addition, this apparent reverse recovery power only decreases slightly with decreasing forward current. When using a typical diode, reducing the forward current from 6000 A to 100 A, that is, 60 times, can reduce the apparent reverse recovery power by only 2 times. As a result, the reverse diode under this condition will be most prone to failure during reverse recovery due to the low level of forward current.

Next in order, the following describes the control of the reverse recovery current using a saturable core, which is disclosed in the following patent documents:

(a) in Japanese Patent No. JP-3745561-B2 (which is hereinafter referred to as the second patent document) and

(b) in US patent No. 6392907, which relates to the family of the second patent document.

A second patent document discloses a forced-commutated inverter that utilizes saturable core reverse recovery control. In the inverter, one or two saturable cores cut off the current flowing into at least one of the two DC coupling capacitors. During reverse recovery of the reverse diode, the reverse recovery current is set exclusively by the fixing circuit, which contains a clamp capacitor, a clamp diode, and clamp resistors.

For this application, low loss saturable cores are usually chosen. In magnetic flux B with intensity H of the electric field characteristic of the saturated core, the saturated core acts on a small magnetic field, and switching is caused between two extreme saturation states corresponding to the maximum magnetic flux B _max and the minimum magnetic flux B _min . This results in low loss generation. Thus, the accumulation of a large amount of energy in the anode electric reactor is prevented.

However, when introducing such saturable cores, in particular a three-phase three-level inverter of the prior art containing saturable cores, another related problem arose. When the voltage of the DC coupling capacitor is charged with current from a different phase, the saturable cores of the three-level inverter receive an electric current based on the bias currents flowing in the fixing capacitors, and then these saturable cores are switched to the corresponding saturation state. Thus, saturable cores can be set in a state directly opposite to that which is necessary to protect the reverse diode during reverse recovery. In this case, the reverse recovery current flowing in the reverse diode will increase at a high value of dI / dt, which is most likely to cause the failure of the reverse diode.

In a high power inverter circuit using linear anode electric reactors, the problem arises of using high inductance to meet the requirements of typical high voltage reverse diodes. During each switching cycle, a significant amount of energy is accumulated and released in such electric reactors, which makes a significant contribution to the total losses of the inverter. In addition, a high power inverter circuit using linear anode electric reactors provides a purely inductive load on the high voltage reverse diodes. Such a purely inductive load has the greatest harmful effect on these reverse diodes. In this case, situations of the presence of the most serious harmful effects are observed at a low load current, which, therefore, impedes the need for using undesirably high inductance values.

High power inverters of the prior art, each using saturable cores, contain cores with two well-defined saturation states. As a result, high power converters that use quick-turn-on devices, such as, for example, gate-switched valves (GCTs), IGBTs or IGBTs (IEGTs) There is a risk of overload during reverse recovery due to the erroneous setting of the core saturation state.

The main objective of the present invention is to provide an inverter device with forced switching, which, in actual use, is capable of performing well-defined operations in almost any environment with reliable control of the reverse current of the diode recovery.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a high-power forced-switching inverter device having a maximum nominal output current I _Rout , including at least one DC coupling capacitor, at least one anode dissipation inductance, at least one shoulder of the switch, at least one level locking circuit, and at least one block with a saturable core. The DC coupling capacitor has a ripple voltage characterized by a maximum value dV _{m of the} absolute value of the slew rate dV _DC / dt, which satisfies the relation -dV _m ≤ dV _DC / dt≤dV _m , and the anode dissipation inductance is connected in series with the coupling coupling DC coupling . The switch arm comprises a series connection of at least one lockable valve device and at least one return diode, and the level locking circuit comprises at least one fixing capacitor, at least one fixing diode, and at least at least one voltage level latching circuit, which contains at least one resistor.

A forced-switching high-power inverter device is characterized in that the saturable core unit has one of the linear saturation characteristics and smooth saturation characteristics, each of which has a saturation current equal to I _sat , and the saturation current I _{sat is} set so that it is large than the bias current created due to the slew rate dV _m , with a capacitance C ₃₁ of at least one fixing capacitor, so that the relation from the equation below is satisfied:

I _Rout > I _sat > C ₃₁ × dV _m

Since in the aforementioned high-power forced-switching inverter device, a saturable core unit is used in a forced-switching inverter device that has a built-in clearly defined initial state and forced action, well-defined operation can be realized under actual use in almost any conditions. As a result, reliable control of the reverse recovery current of the diode can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawing of FIG. 1A is a circuit diagram showing a configuration of a circuit of a large power circuit breaker with a forced switching according to a first preferred embodiment of the present invention.

In the drawing of FIG. 1B is a circuit diagram showing a configuration of a two-level, high power, forced-switching inverter according to a first preferred embodiment of the present invention.

In the drawing of FIG. 1C is a circuit diagram showing a configuration of a three-level, high power, forced-commutated inverter according to a first preferred embodiment of the present invention.

In the drawing of FIG. 1D is a graph showing the electrical characteristic of the voltage integral over time ∫Vdt versus current I of each of saturable core blocks 5a, 5b and 5c shown in the drawings of FIG. 1A, FIG. 1B and FIG. 1C, and their saturation current I _sat .

In the drawing of FIG. 2A is a graph showing the electrical characteristic of the voltage integral over time ∫Vdt versus current I for each of the saturable core units 5a, 5b and 5c shown in the drawings of FIG. 1A, FIG. 1B and FIG. 1C, along with the determination of the integral of their voltage over time at saturation ∫Vdt _sat , according to a second preferred embodiment of the present invention.

In the drawing of FIG. 2B is a graph showing the relationship between the reverse recovery charge Q _rr and the forward current I flowing in a typical high-voltage high-power silicon diode at an elevated transition temperature.

In the drawing of FIG. 2C is a waveform diagram showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I _{22 of} diode 22 , for use in the two-level high power inverter of FIG. 1B in the case when the output current I _out = 100 A.

In the drawing of FIG. 2D is a timing diagram of the signals showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b in them, and (c) voltage V ₂₂ and current I _{22 of} diode 22 , for use in the two-level high power inverter of FIG. 1B in the case when the output current I _out = 400 A.

In the drawing of FIG. 2E is a waveform diagram showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I _{22 of} diode 22 , for use in the two-level high power inverter of FIG. 1B in the case when the output current I _out = 1000 A.

In the drawing of FIG. 2F is a waveform diagram showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I _{22 of} diode 22 , for use in the two-level high power inverter of FIG. 1B in the case when the output current I _out = 3000 A.

In the drawing of FIG. 2G is a waveform diagram showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I _{22 of} diode 22 , for use in the two-level high power inverter of FIG. 1B in the case when the output current I _out = 6000 A.

In the drawing of FIG. 2H is a graph showing the calculated dependence of the anode voltage on the anode current of the diode 22 for each shutdown, where the parameter is the output current I _out .

In the drawing of FIG. 2I is a graph showing a calculated dependence of reverse recovery power on the anode voltage of diode 22, where the parameter is the output current I _out .

In the drawing of FIG. 2J is a graph showing the calculated dependence of the reverse recovery power causing the harmful effect on the output current I _{out of} diode 22 for various circuit configurations and the corresponding settings of the voltage integral over time at saturation ∫Vdt _sat .

In the drawing of FIG. 3A is a block diagram showing a saturable core unit 5a according to a third preferred embodiment of the present invention.

In the drawing of FIG. 3B is a perspective view showing the appearance of the saturable core unit 5a of FIG. 3A.

In the drawing of FIG. 4 is a circuit diagram showing a configuration of a high power inverter with forced switching according to a fourth preferred embodiment of the present invention.

In the drawing of FIG. 5A is a circuit diagram showing a configuration of a saturable core unit 5a for use in a forced switching high power inverter according to a fifth preferred embodiment of the present invention.

In the drawing of FIG. 5B is a first portion of the signal timing diagram in the unbalanced case, showing (a) the current I _5a of the saturated core unit 5a and (b) the inductance current I _{71 of} 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A.

In the drawing of FIG. 5C is a second portion of the signal timing diagram in the unbalanced case, showing (a) the current I _5a of the saturated core unit 5a and (b) the inductance current I _{71 of} 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A.

In the drawing of FIG. 5D is a first portion of the signal timing diagram, in the preferred case, showing (a) the current I _5a of the saturated core unit 5a and (b) the inductance current I _{71 of} 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A.

In the drawing of FIG. 5E is a second portion of the signal timing diagram in the preferred case, showing (a) the current I _5a of the saturated core unit 5a and (b) the current I _{71 of the} inductance 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A.

In the drawing of FIG. 6A is a circuit diagram showing a configuration of a high power inverter with forced switching according to a sixth preferred embodiment of the present invention.

In the drawing of FIG. 6B is a waveform diagram showing the voltage V _5a of the saturated core unit 5a of FIG. 6A, as well as voltage V ₂₂ and current I ₂₂ of the reverse current diode 22 of FIG. 6A, when the level locking circuit 3 comprises a clamping resistor 331 with a typical scattering inductance 331a of a clamping resistor of 1.5 μH (microgenry).

In the drawing of FIG. 6C is a waveform diagram showing the voltage V _5a of the saturated core block 5a of FIG. 6A, as well as voltage V ₂₂ and current I ₂₂ of the reverse current diode 22 of FIG. 6A, when the reverse recovery current of the diode is amplified immediately at the very beginning, and damping is added to the dissipation inductance of the fixing resistor 331a.

In the drawing of FIG. 7A is a circuit diagram showing a configuration of a high power, high power inverter according to a seventh preferred embodiment of the present invention.

In the drawing of FIG. 7B is a timing diagram of signals in the case without any delay causing core 336, showing voltage V _5a of the saturated core unit 5a, voltage V _5b of the saturated core unit 5b, voltage V ₂₂ and current I ₂₂ of the reverse current diode 22, and current I ₃₃ circuit 33 reset voltage level fixation.

In the drawing of FIG. 7C is a timing diagram of signals in the case of a delay causing core 336 showing the voltage V _5a of the saturated core unit 5a, voltage V _5b of the saturated core unit 5b, voltage V ₂₂ and current I ₂₂ of the reverse current diode 22, and current I ₃₃ circuit 33 reset voltage level fixation.

BEST MODE FOR CARRYING OUT THE INVENTION

The following is a description of preferred embodiments of the invention with reference to the attached drawings. Similar components or elements are denoted by the same reference numbers.

FIRST PREFERRED EMBODIMENT OF THE INVENTION

In the drawing of FIG. 1A shows a configuration of a circuit of a large power circuit breaker according to a first preferred embodiment of the present invention. In the drawing of FIG. 1B shows a configuration of a two-level, high power, forced switching inverter according to a first preferred embodiment of the present invention. In the drawing of FIG. 1C shows a configuration of a three-level, high power, forced-switching inverter according to a first preferred embodiment of the present invention, and FIG. 1D shows the electrical characteristic of the voltage integral over time ∫Vdt versus current I for each of the saturable core blocks 5a, 5b and 5c shown in FIG. 1A, FIG. 1B and FIG. 1C, and their saturation current I _{sat is} shown.

CIRCUIT DIAGRAM

With reference to FIG. 1A, a chopper circuit according to this preferred embodiment of the invention has input terminals T1 and T2 and an output terminal T11. The chopper circuit includes a DC coupling capacitor 11, a switch arm 2, a level fixing circuit 3, a scattering anode inductor 41, a saturable core unit 5a, and a controller 91. The switch arm 2 comprises a series circuit of a shut-off valve device 21, which is, for example, a valve commutated by a control electrode (GCT), transistor with an insulated gate and increased injection (IEGT) or a bipolar transistor with an insulated gate (IGBT), and a reverse diode 22. The circuit 3 of the level lock contains a fixed a capacitor 31, a clamping diode 32, and a clamp level reset circuit 33, which includes a clamping resistor 331. The controller 91 periodically generates and outputs a voltage signal for controlling the gate to the valve of the device 21, the shutoff valve.

In the chopper circuit, a DC coupling capacitor 11 is connected between the input terminals T1 and T2. The input terminal T1 is connected via an anode leakage inductance 41 to one end of the switch arm 2 and to one end of the level fixing circuit 3. On the other hand, the input terminal T2 is connected via a saturable core unit 5a to the other end of the switch arm 2 and to the other end of the level locking circuit 3.

In this case, the saturated core unit 5a can control the reverse recovery current flowing from the return diode 22 to the DC coupling capacitor 11. The dissipation anode inductance 41 may be a separate element that is designed to limit the current flowing from the DC coupling capacitor 11 through the device 21, a shut-off valve, a return diode 22, and a saturated core unit 5a. However, the anode dissipation inductance 41 can also be reduced to a very low value of the dissipation inductance of the bus.

The following is a description of the operation of the circuit breaker.

State 1: Lockable valve device 21 is open

When the shut-off valve device 21 is in the open state, a load current flows from the input terminal T1, which is referred to as the “P terminal (positive terminal)”, through the anode leakage inductance 41 and the shut-off valve device 21 to the output terminal T11. In this case, the reverse diode 22 is locked. Depending on the charge in the fixing capacitor 31, current can flow out from the dissipation anode inductance 41 through the fixing capacitor 31, then through the parallel connection circuit of the fixing diode 32 and the fixing level voltage reset circuit 33, and then through the saturated core block 5a to the input terminal T2, which referred to as “terminal N (Negative terminal)” until the voltage across the latch capacitor 31 is equal to the voltage across the DC coupling capacitor 11. After that, the voltage at the saturable core unit 5a becomes equal to zero, and the current flow stops. According to FIG. 1D, the saturable core unit 5a reaches a near-center position of its characteristic shown in FIG. 1D corresponding to the so-called magnetization curve. Thus, a complete reset of the saturable core unit 5a and the fixing capacitor 31 to the initial state is achieved.

State 2: locking device 21 lockable valve

When the locking device 21 of the lockable valve is locked, some excess voltage will appear on its terminals due to the anode inductance 41 of the dissipation. The level fixing circuit 3 is closely connected by a wire connection to a circuit having a small parasitic inductance, for example 200 nH (nanogenry) or 400 nH. In this case, the current flowing out of the lockable valve device 21 will be switched into a level lock circuit 3, where the same current mainly flows in the clamp capacitor 31 and in the clamp diode 32. Then, the same current flows in the return diode 22 and is output through the output terminal T11.

State 3: steady state when locking device 21 lockable valve

As the output current I _out continues to flow, the fixing capacitor 31 is charged to a higher level, causing a negative potential to occur at the output terminal T11. Accordingly, the saturable core unit 5a receives and accumulates the same voltage, creating a voltage integral времениVdt over time, and this leads to a conducted current according to FIG. 1D. If the output current I _{out of the} load is greater than the saturation current I _sat of the saturable core unit 5a, as shown in FIG. 1D, then the saturable core unit 5a enters the saturation state and switches the voltage at its terminals so that it becomes zero. If I _out <I _sat , then the saturable core unit 5a remains in the linear and unsaturated region of the characteristic of FIG. 1D and exhibits equivalent inductance as its circuit, but also reduces the voltage at its terminals to zero, keeping the value of the voltage integral over time ∫Vdt equal to the value in equilibrium.

State 4: turning on the lockable valve device 21

After turning on the shut-off valve device 21, the current I _out will again be connected to the input terminal T1. The reverse diode 22 receives a reverse bias and, therefore, the reverse recovery current flows. This causes the current direction in the saturable core block 5a to become reverse and, according to FIG. 1D, voltage appears at its terminals. This causes an inductive current to flow in the saturable core unit 5a until the opposite saturation is achieved. As a result of this, such a current will have an almost constant small value dI / dt determined by the equivalent inductance L _equ of the saturated core unit 5a in the unsaturated region of the characteristic of FIG. 1D.

In contrast to such equivalent inductance, the level locking circuit 3 directly delivers a current change to the arm 2 of the switch with a high dI / dt value. This leads to the removal of charge carriers from the reverse diode 22, which then receives a reverse bias. In this case, the load recovery characteristic of the reverse recovery for the reverse diode 22, mainly determines the circuit 33 reset voltage level fixation. Therefore, due to the fact that the level fixing circuit 3 provides for the presence of a purely fixing resistor 331, the state of the resistive load during reverse recovery is obtained in the return diode 22.

During this reverse recovery time period, a saturable core unit 5a accumulates some time integral напряженияVdt over time, and, according to FIG. 1D, it creates some current. When the reverse recovery current flows, the saturable core unit 5a drops the charge of the fixing capacitor 31 and returns to a state corresponding to almost the center of the saturation characteristic of FIG. 1D.

TWO-LEVEL INVERTER

With reference to FIG. 1B, a two-level inverter with forced switching in addition to the components shown in FIG. 1A further comprises the following components:

(a) a lock valve device 23 that is connected in parallel with the return diode 22,

(b) a reverse diode 24, which is connected in parallel with the device 21 of the shut-off valve,

(c) a saturable core block 5b having a characteristic similar to that of a saturable core block 5a that is inserted between the input terminal T1 and the diffuse anode inductance 41, and

(d) a controller 92, which generates and outputs voltage signals for controlling the valve, respectively supplied to the valves of the shut-off valve devices 21 and 23, for alternately locking the shut-off valve devices 21 and 23.

In this case, instead of the switch arm 2 of FIG. 1A, a switch arm 2b is provided, comprising two diodes 22 and 24. Controlling a portion of the reverse recovery current of each of the return diodes 22 and 24 coming from the DC coupling capacitor 11 provides at least one of the saturable blocks 5a and 5b the core. As shown in FIG. 1B, the two-level inverter circuit is symmetrical, the same circuit may receive a positive load current output to the external circuit, and may receive a negative load current that flows to the internal circuit. The operation of a two-level inverter is very similar to the operation, the explanation of which is given in relation to the circuit breaker of FIG. 1A, for both directions of the load current, with one exception, the explanation of which is given below for the positive load current.

When the shut-off valve device 21 is brought into the open state, the power to its anode does not come directly from the DC coupling capacitor 11 through the dissipation anode inductance 41, similar to what happens in the chopper shown in FIG. 1A. Instead, a saturable core block 5b is connected to this line, and it is in the central position of the characteristic of the saturable core block 5b shown in FIG. 1D, because before this moment there was no current. As a result of this, the lock valve device 21 mainly conducts the current coming from the level fixing circuit 3 until the saturable core unit 5b is saturated, whereby the lock valve device 21 is connected to the DC coupling capacitor 11 .

THREE-LEVEL INVERTER

With reference to FIG. 1C, a three-level forced-switching inverter comprises a switch arm 2c instead of the switch arm 2b of FIG. 1B and further comprises an input terminal T3, a saturable core unit 5c, a level fixing circuit 6, and a dissipation anode inductance 42 in addition to those elements shown in FIG. 1B. In addition, the three-level inverter with forced switching contains a controller 93, designed to control devices 21, 23, 25 and 27 of the shut-off valve instead of the controller 92 of FIG. 1B. As shown in FIG. 1C, a DC coupling capacitor 11 is connected between the input terminals T1 and T3, and a DC coupling capacitor 12 is connected between the input terminals T2 and T3. The input terminal T3 is connected via a saturable core unit 5a to level lock circuits 3 and 6 and to the switch arm 2c. The input terminal T2 is connected via a saturable core block 5c to the switch arm 2c. The level fixing circuit 6 includes a fixing capacitor 61, a fixing diode 62, and a fixing level voltage reset circuit 63 containing a resistor 631.

The switch arm 2c contains not only four diodes 21, 23, 25 and 27 for locking the valve, but also six reverse diodes 22, 24, 26, 28, 291 and 292 for use in a typical three-level inverter, namely they include a reverse diode 22, reverse diode 24, reverse diode 26, reverse diode 28, reverse zero point diode 291, and reverse zero point diode 292. Among these reverse diodes 22, 24, 26, 28, 291 and 292, two reverse diodes 22 and 28 do not receive reverse recovery current in the inverter. The other four reverse diodes 24, 26, 291 and 292 can receive reverse recovery current from at least one of the DC coupling capacitors 11 and 12.

Such reverse recovery current will flow through line P through input terminal T1 when reverse diode 24 receives reverse recovery current, flow through line C through input terminal T3 when reverse zero diode 291 or reverse zero diode 292 receive reverse recovery current , or flow along the N line when the reverse diode 26 receives the reverse recovery current. As a consequence, at least one of the saturable core blocks 5a, 5b, and 5c is located in each of these lines P, C, and N. The three-level inverter of FIG. 1C operates similarly to the two-level inverter of FIG. 1B.

OTHER MULTI-LEVEL INVERS

In the drawings of FIG. 1A, FIG. 1B and FIG. 1C illustrates the most widely used high power forced-switching inverters, but the present invention is not limited to them. Other multilevel inverters may be provided comprising the same saturable core units 5a, 5b and 5c.

RISK OF HAZARDOUS INFLUENCE ON THE DIODE TO UNDERSTAND THE CHARACTERISTIC AT THE LOWER LIMIT OF THE SATURATION CURRENT I _sat

However, the reverse diodes 24 and 26 and / or the reverse zero point diodes 291 and 292 can be exposed to dangerous harmful effects during reverse recovery if the saturated core units 5a, 5b and / or 5c are not in the correct saturation state before turning on the device 21, 23, 25, and 27 of the lockable valve. Such an incorrect magnetization state may occur due to the current flowing in the saturable core blocks 5a, 5b and / or 5c caused by the reset of the fixing capacitor 31 or 61.

The abnormal saturation state may also result from a bias current flowing to the clamp capacitor 31 having a capacitance C ₃₁ , or to the clamp capacitor 61 having a capacitance C ₆₁ . Such a bias current occurs due to a change in voltage across the DC coupling capacitor 11 or 12. The maximum value of this current is calculated according to the equation I _dis = C ₃₁ × dV _m or I _dis = C ₆₁ × dV _m , where dV _m denotes the maximum value of the absolute value of the voltage rise rate on the coupling capacitor 11 for direct current or on the capacitor 12 for coupling constant current. Therefore, the slew rate dV _m satisfies the following relation -dV _m ≤dV _DC / dt≤dV _m , where dV _DC / dt is the slew rate of the voltage across the DC coupling capacitor 11 or 12.

Essentially, it seems that there is no way to prevent such a bias current from affecting the saturation state of the saturated core unit 5a, 5b, or 5c. However, you must make sure that the core block will not approach an unsatisfactory saturation state. Because of this, a self-returning characteristic is needed that can return a saturation state to a well-defined safe position under all circumstances.

Such a return characteristic is absent in the core characteristic of the prior art, which can provide only one stable saturation state in any extreme position. Instead, the linear region shown in FIG. 1D, or at least a curved, smooth region between saturation limit values to determine the return level directly between both saturation limit values.

In addition, the reset of the voltage of the fixing capacitor and the transfer of any bias current must be performed in such a way as to achieve a sufficient distance to saturation when one of the devices 21, 23, 25, or 27 of the shut-off valve is turned on. Therefore, the saturation current I _sat must be selected at least so that it is greater than the maximum value of all such bias currents flowing in the saturated core block 5a, 5b or 5c, satisfying the following relation: Isat> I _dis = C ₃₁ × dV _m or I _sat > I _dis = C ₆₁ × dV _m .

In addition, it is obvious that it is preferable when the saturable core unit 5a, 5b or 5c retains at least 75% of its rated isolation capacity when it experiences the strongest current load equal to I _dis = C ₃₁ × dVm or I _dis = C ₆₁ × dV _m . As a result of this, the following equation must be specified:

I _sat > 4 × I _dis = 4 × C ₃₁ × dV _m , or

Isat> 4 × I _dis = 4 × C ₆₁ × dV _m

UNDERSTANDING THE TOP LIMIT FOR A SATURATION CURRENT I _sat

Essentially, the conditions explained above can be easily satisfied by choosing a very high value for the saturation current I _sat . However, a saturable core unit 5a, 5b, or 5c will store energy E in an unsaturated state in exactly the same way as a linear inductor does. If such an unsaturated state exhibits a purely linear characteristic, then such energy E can be calculated according to the following equation:

E = 1/2 × L _equ × I ² ,

where L _equ denotes the equivalent inductance of a saturable core block 5a, 5b or 5c, which is L _equ = V / (dI / dt) = ∫ Vdt _sat / I in such a linear mode. When saturation is reached, the energy accumulated at this point in time is captured. In this case, this energy value E _sat becomes equal to Esat = 1/2 × L _equ × I _sat ² . It is released into the circuitry when subsequently the core unit is again taken out of this saturation state.

Since it has been established that one of the main disadvantages of the prior art is the large amount of stored energy, a low amount of stored energy is required to ensure low inverter losses. As a consequence, a prerequisite is to set a small value of the saturation current I _sat . It must be set lower than the maximum rated output current I _Rout in order to achieve a saturation state under any circumstances as follows: 0 <I _sat <I _Rout . In addition, to achieve a low level of stored energy, it is highly preferable that the level is below 20% of the maximum rated output current, so that the following inequality holds:

0 <I _sat <I _Rout / 5

CALCULATION EXAMPLES

Finally, examples of calculation based on the values obtained in practice, which are described below, will be given.

The high-power inverter has a maximum rated output current I _Rout = 6000 A, nominal DC coupling voltage V _DC = 3500 V and an average switching frequency of 400 Hz. Each of the DC coupling capacitors 11 and 12 can correspond to a normal value that allows voltage ripples of approximately ± 10% at the nominal peak output current, the limit value of which is usually set for safety reasons I _Noutpeak = I _Rout / 1,5 = 4000 A. As a result, a dc DC link voltage change rate of dV _DC / dt≤ (3500 [V] × 2 × 10%) / 1.25 [milliseconds] = 560 [volt / millisecond (V / ms)] = dV _m . In such an inverter, it may usually be required that the capacitance of the fixing capacitor 31 is C ₃₁ = 20 μF. In such a case, in a first preferred embodiment of the invention, a ratio of 4 × C ₃₁ × dV _m = 4 × 20 [μF] × 560 [volt / millisecond (V / ms)] = 44.8 [A] <I _sat while for the preferred upper limit I _sat <6000 A / 5 = 1200 A.

SECOND PREFERRED EMBODIMENT OF THE INVENTION

With reference to the drawings of FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I and FIG. 2J, the additional characteristics of a saturable core unit 5a, 5b, and 5c that can be used in an inverter from a first preferred embodiment of the invention, used to create a high-power forced-switching inverter according to a second preferred embodiment of the present invention, are demonstrated and explained.

In the drawing of FIG. 2A is a graph showing the electrical characteristic of the time integral of the voltage integral напряженияVdt versus current I for each of the saturable core blocks 5a, 5b and 5c shown in the drawings of FIG. 1A, FIG. 1B and FIG. 1C, along with the determination of the integral of their voltage over time at saturation ∫Vdt _sat , according to a second preferred embodiment of the present invention. In the drawing of FIG. 2B is a graph showing the relationship between the reverse recovery charge Q _rr and the forward current I flowing in a typical high-voltage high-power silicon diode at an elevated transition temperature.

In addition to this, in the drawing of FIG. 2C is a signal timing diagram showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I ₂₂ diode 22, for use in a two-level high power inverter from FIG. 1B in the case where the output current I _out = 100 A. In the drawing of FIG. 2D is a timing diagram of the signals showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b in them, and (c) voltage V ₂₂ and current I ₂₂ diode 22, for use in a two-level high power inverter from FIG. 1B in the case where the output current I _out = 400 A. In the drawing of FIG. 2E is a timing diagram of the signals showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I ₂₂ diode 22, for use in a two-level high power inverter from FIG. 1B in the case where the output current I _out = 1000 A. In the drawing of FIG. 2F is a timing diagram of the signals showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I ₂₂ diode 22, for use in a two-level high power inverter from FIG. 1B in the case where the output current I _out = 3000 A. In the drawing of FIG. 2G is a timing diagram of the signals showing (a) voltages V _5a and V _5b of saturable voltage blocks 5a and 5b, (b) normalized magnetic flux F _5a and F _5b therein, and (c) voltage V ₂₂ and current I ₂₂ diode 22, for use in a two-level high power inverter from FIG. 1B in the case where the output current I _out = 6000 A. In particular, in the drawings of FIG. 2C-FIG. 2G shows the signals observed during switching of the load current from the return diode 22 to the shut-off valve device 21, at different values of the positive load current in the two-level inverter of FIG. 1B, having a maximum nominal output I _Rout = 6000 A and a voltage integral over time at saturation ∫Vdt _sat = 2.4 millivolts × second, as well as at a transition temperature of the reverse diode 22 set to its maximum allowable value.

In addition, in the drawing of FIG. 2H is a graph showing the calculated dependence of the anode voltage on the anode current of the diode 22 for each shutdown, where the parameter is the output current I _out , for the conditions shown in the drawings of FIG. 2C-FIG. 2G. In the drawing of FIG. 2I is a graph showing the calculated dependence of the reverse recovery power on the anode voltage on the diode 22, where the parameter is the output current I _out . In FIG. 2J is a graph showing the calculated dependence of the reverse recovery power causing the harmful effect on the output current I _{out of the} diode 22 for various circuit configurations and the corresponding settings of the saturation voltage integral over time ∫Vdt _sat , in particular in FIG. Figure 2J shows the dependence of the highest value of reverse recovery power at a reverse voltage of 3.5 kV or higher, which is hereinafter referred to as the "reverse recovery power causing harmful effects", on the output current I _{out of the} inverter, observed in various modes of the inverter circuit:

(1) curve 101 shows the reverse recovery power causing a harmful effect when using the prior art circuit with a linear anode electric reactor 41 having an inductance L ₄₁ equal to 7 μH;

(2) curve 102 shows the power of the reverse recovery, which causes a harmful effect, in the case when the voltage integral over time at saturation ∫Vdt _sat = 0.6 millivolts × second, and the inductance L ₄₁ = 1 μH;

(3) curve 103 shows the power of the reverse recovery, which causes a harmful effect, in the case when the voltage integral over time at saturation ∫Vdt _sat = 1.2 millivolts × second, and the inductance L ₄₁ = 1 μH;

(4) curve 104 shows the power of reverse recovery, which causes a harmful effect, in the case when the voltage integral over time at saturation ∫Vdt _sat = 2.4 millivolts × second, and the inductance L ₄₁ = 1 μH;

(5) curve 105 shows the power of the reverse recovery, which causes a harmful effect, in the case when the voltage integral over time at saturation милVdt _sat = 3.6 millivolts × second, and the inductance L ₄₁ = 1 μH;

(6) curve 106 shows the power of the reverse recovery, which causes a harmful effect, in the case when the voltage integral over time at saturation ∫Vdt _sat = 4.8 millivolts × second, and the inductance L ₄₁ = 1 μH; and

(7) curve 107 shows the permissible reverse recovery power, causing harmful effects, adapted to the anode electric reactor. In the circuit breaker of the prior art without the saturable core unit 5a of FIG. 1A, the values for curve 107 were obtained experimentally using an adapted linear anode electric reactor for each set value of the current loading the diode to its full capacity at that set value of the anode current.

In the drawing of FIG. 2A shows a typical hysteresis loop observed with a saturable core unit 5a from the first preferred embodiment of the invention. In this case, the voltage integral over time at saturation ∫Vdt _sat is determined by the value at saturation, which is characterized by the fact that the block with the core is in a state with low inductance.

Such a characteristic, showing an almost constant slope in the unsaturated state and another, very small slope in the saturation state, can be obtained by means of a single core or by a set of cores, all of which have the same characteristics. However, a core block having a gradient change in inductance can also be used. Such a core block can be obtained using a series connection of blocks with cores that have different characteristics, or using the appropriate material from which the core is made. In addition, in this case, the saturation integral is defined as the highest attainable value of ∫Vdt in real conditions.

In the drawing of FIG. 2B shows a reverse recovery charge as a function of forward current for a typical high voltage silicon diode. The dependency is highly nonlinear. In this case, at low current there is a large charge per ampere of direct current flowing in the diode.

In the drawings of FIG. 2C-FIG. 2G shows the results obtained with the diode used in the two-level inverter of the second preferred embodiment of the invention, for different values of the output current I _{out of the} inverter. In FIG. 2C shows the result with an output current I _out = 100 A, FIG. 2D shows the result with the output current I _out = 400 A, in FIG. 2E shows the result with an output current I _out = 1000 A, FIG. 2F shows the result with an output current I _out = 3000 A and in FIG. 2G shows the result with the output current I _out = I _Rout = 6000 A. In these cases, in the upper graph of each of the drawings of FIG. 2C-FIG. 2G shows the voltage V _5a on the saturated core unit 5a and the voltage V _5b on the saturated core unit 5b. On the average graph of each of the drawings of FIG. 2C-FIG. 2G shows a magnetic flux F _5a in a saturated state of a saturable core unit 5a and a magnetic flux F _5b in a saturated state of a saturable core unit 5b. In the lower graph of each of the drawings of FIG. 2C-FIG. 2G shows the anode current I ₂₂ flowing in the return diode 22 and the anode voltage V ₂₂ on the return diode 22. Each of the saturable core units 5a and 5b has a voltage integral over time at saturation ∫Vdt _sat = 2.4 millivolts × second and saturation current I _sat = 160 A; therefore, it has an equivalent inductance L _equ = 15 μH.

With reference to FIG. 2C, both blocks: a saturable core block 5a and a saturable core block 5b start functioning from zero voltage at time t = 334 microseconds. At this point, the saturated core block 5b has a saturation level of zero, while the saturated core block 5a has a saturation level of ∫Vdt = 0.62 × ∫Vdt _sat . At this time t = 334 microseconds, the reverse diode 22 has a direct bias, as a result of which the anode current I ₂₂ = 100 A and the anode voltage V ₂₂ = 1.5 V. When the device 21 of the shut-off valve is turned on, at time t = 335 microseconds both block: block 5a with a saturated core and block 5b with a saturated core receive the corresponding voltage, and this leads to a change in the saturation state of both blocks, and the reverse diode 22 receives a negative anode current I ₂₂ . In this case, such an anode current I ₂₂ arises mainly from the level fixing circuit 3, and it rapidly increases, almost reaching I ₂₂ = 1 kA (kiloampere). However, such a large anode current is applied to the return diode 22 only in a state of relatively low anode voltage, and after some time, at time t = 336 microseconds, the anode current I ₂₂ may already decrease, while the anode voltage V ₂₂ on the reverse diode 22 slowly approaches the value of the voltage across the capacitor 11 DC coupling of, for example, V _DC = 3650 V. throughout this period of time the two blocks: block saturable core 5a and 5b block saturable core remain in the unsaturated state, bespechivaya total inductance equal to 2 × L _equ = 30 mH for electrical insulation or isolation shoulder switch 2b of Fig. 1B from the DC coupling capacitor 11.

With reference to the drawing of FIG. 2D, with the output current I _out = 400 A, the saturable core unit 5a starts functioning already with a saturation voltage level of ∫Vdt = 1 × ∫Vdt _sat , as a result of which the saturable core unit 5a was already completely saturated. In this case, the saturable core unit 5b first changes the saturation state to a full saturation state. The saturated core block 5a is turned on later, then the unsaturated region completely passes through and reaches the opposite saturation at time t = 941 microseconds. Thus, the reverse diode 22 does not receive any current from the DC coupling capacitor 11, since the saturable core unit 5a ensures its isolation until the anode voltage V ₂₂ reaches the DC voltage level V _DC = 3650 V and the reverse recovery current will not be zero. Therefore, an inductance of 1 × L _equ = 15 μH is _provided for decoupling the switch arm 2b from the DC coupling capacitor 11 when the diode goes into a state in which a high voltage is applied to it.

With reference to the drawing of FIG. 2E, with the output current I _out = 1000 A, the saturated core unit 5a starts functioning again at full saturation. Saturated core blocks 5a and 5b become active one after the other. The saturable core unit 5a now reaches full saturation already at time t = 1540 microseconds, i.e. approximately 4 microseconds before the end of the trailing edge of the diode current. As a result, the DC coupling capacitor 11 at this point in time is directly connected to the reverse diode 22 and, therefore, its anode current I ₂₂ increases slightly.

With reference to the drawing of FIG. 2F, with an output current I _out = 3000 A, both blocks: block 5a with a saturable core and block 5b with a saturable core act even faster, and the reverse recovery current flows for a longer time. As a result, the saturable core unit 5a has already reached the saturation state 7.5 microseconds before the end of the trailing edge of the diode current, which therefore leads to a significant increase in the anode current I ₂₂ .

With reference to the drawing of FIG. 2G, with an output current I _out = 6000 A, this effect is even more noticeable. However, even in this case, the anode voltage V _{22 has} reached the value V ₂₂ = 2 kV when the reverse diode 22 is connected to the DC coupling capacitor 11. Despite the small inductance of the circuit provided by the anode inductance 41 of the scattering, which is, for example, L = 1 μH, the slew rate dI ₂₂ / dt of the anode current I ₂₂ is very small and the anode current I ₂₂ remains such that I ₂₂ <2000 A.

In the drawing of FIG. 2H, the corresponding reverse recovery work areas are estimated by plotting the anode voltage V ₂₂ as a function of the anode current I ₂₂ for each reverse recovery of the reverse diode 22. This estimate shows that at high anode voltage during reverse recovery in the range from low to medium forward currents I _out = 100 A and 400 A, the anode current is low.

In the drawing of FIG. 2I shows the next evaluation step. It shows the product of reverse recovery voltage and reverse recovery current, that is, reverse recovery power, as a function of reverse recovery voltage or anode voltage V ₂₂ . In cases where the output current is I _out = 100 A and I _out = 400 A, the magnitude of the reverse recovery power at an anode voltage of V ₂₂ = 3.5 kV is small. In this case, the two-level inverter circuit according to the second preferred embodiment of the invention fully protects the reverse diode 22 under these conditions.

In the drawing of FIG. Figure 2J shows another evaluation stage, namely, a comparison by plotting the power of the reverse recovery causing harmful effects as a function of the inverter output current I _out for various circuit configurations and various settings of the voltage integral over time at saturation ∫Vdt _sat . In this case, the harmful effect on the diode during reverse recovery in the mode of maximum design load from the prior art is shown in FIG. 2J by dashed curve 101. From the graph shown in FIG. 2J, the following is clear: as for curve 101, the small set value of the voltage integral over time at saturation ∫Vdt _sat compared to the voltage integral over time at saturation ∫Vdt _sat = 0.6 millivolts × second shown on curve 102 can already reduce the harmful effect on the diode in the case of a smaller anode current I ₂₂ . However, in the case of a higher anode current I ₂₂ , when switching to the anode current I ₂₂ = 400 A, the harmful effect on the diode is stronger than that shown on curve 101.

Setting the voltage integral over time at saturation ∫Vdt _sat = 1.2 millivolts × second, as shown in curve 103 of FIG. 2J reduces the harmful effect on the diode below the level observed in the circuit of the prior art, which corresponds to curve 101, for all current values less than 2800 A.

Setting the voltage integral over time at saturation ∫Vdt _sat = 2.4 millivolts × second, as shown in curve 104, leads to a reduced level of harmful effects in the entire operating range.

Setting the voltage integral over time at saturation ∫Vdt _sat = 3.6 millivolts × second, as shown in curve 105, or ∫Vdt _sat = 4.8 millivolts × second, as shown in curve 106, leads to a very low level of harmful effects during all working range.

Therefore, the sought value for the time integral of the voltage at saturation ∫Vdt _{sat is} obtained from FIG. 2J. Through curve 107, a permissible reverse recovery power is introduced, causing a harmful effect, adapted to the anode electric reactor, which is referred to as _Prrlar (I). In the case of a circuit breaker of the prior art shown in FIG. 1A, without any saturable core block 5a, curve 107 is a graph of the maximum allowable reverse recovery power causing a harmful effect for the high voltage diode obtained by changing the anode electric reactor 41. In this case, for each current value of curve 107, a new value for the anode electric reactor 41 is set so that the reverse diode 22 is loaded to its limit when it is reversed from such a current.

A second preferred embodiment of the present invention is capable of providing good adaptation to these maximum allowable exposure values as follows. When the voltage integral over time at saturation is chosen equal to ∫Vdt _sat = 0.6 millivolt × second, then the reverse recovery power causing the harmful effect, P _rr (I) according to curve 102 is already smaller than the permissible reverse recovery power causing the harmful effect , which is adapted to the anode electric reactor, for such a diode, represented by curve 107 at the total inverter output current I _out in the interval 0≤I _out ≤I _Rout.

According to a second preferred embodiment of the present invention, the value of the saturation voltage integral over time ∫Vdt _{sat is} then chosen so that P _rr (I) ≤1 / 2 × P _rrlar (I) with at least one output current value I _out in the interval 0≤I _out ≤I _Rout . In FIG. 2J curve 106 is close to such a limit that: in the case of I _out = I _Rout = 6000 A, the power P _rrlar (I) on curve 107 is 7.9 MVA (megavolt-ampere), while the power P _rr (I) at curve 106 is 4.1 MVA. In this mode, since the voltage integral over time at saturation ∫Vdt _sat = 4.8 millivolts × second, the recovery of the diode is extremely smooth, but blocks 5a and 5b with a saturated core have become much larger, therefore, a large amount of energy is transferred, respectively, into the circuit 3 fixation level and circuit 6 fixation level.

Thus, the inverter according to the second preferred embodiment of the present invention adapts in a preferred way to the characteristics of typical high power silicon diodes. Applied very small values of the anode inductance 41 and 42 scattering and very small blocks 5a and 5b with a core, which leads to low cost and low losses in the inverter during its operation.

THIRD PREFERRED EMBODIMENT FOR CARRYING OUT THE INVENTION

In the drawing of FIG. 3A is a block diagram showing a saturable core unit 5a according to a third preferred embodiment of the present invention, and FIG. 3B is a perspective view showing the appearance of the saturable core unit 5a of FIG. 3A.

With reference to FIG. 3 shows a saturable core unit 5a, which can be used in the first or second preferred embodiments of the invention to provide a high power, high power, inverter, according to a third preferred embodiment of the invention. In this preferred embodiment, the saturable core unit 5a comprises a saturable inductor 51, where the saturable inductor 51 comprises at least one gap 5g.

A gap 5g of another substance may be introduced into the magnetic circuit of the saturable core unit 5a. In most cases, such a substance in the 5g gap is completely non-magnetic, which depends on the mechanical design of the core, and the substance in the 5g gap may be some kind of plastic or just air.

In this case, the magnetic flux Φ must pass through the core material and through the substance in the gap. In the material from which the magnetic core is made, magnetic induction B = Φ / A, where A is the cross-sectional area through which the magnetic flux Φ penetrates, therefore, it creates a magnetic field H _fe = B / µµ ₀ , while the magnetic field in non-magnetic substance H _air = B / µ ₀ . In this case, to determine the current penetrating through the core, the integral ∫Hds is calculated along the closed loop passing through the core and the gap 5g of the saturated core unit 5a. If the size of the gap 5g is large enough so that the integral ∫Hds is dominant, then the inductance L of the wound coil of its core is approximately L = (μ ₀ n ² A) / l _air , where l _air denotes the thickness of the gap 5g filled with a nonmagnetic substance, and "n" is the number of turns.

The gap 5g is often used in the magnetic cores of inductors or transformers in the presence of a large DC component of the current in such components. The gap 5g is often referred to as the "air gap" and the magnetization curve is changed so as to provide or create an enlarged region having an almost linear dependence of magnetization. Therefore, it is a linear region that must be extended by the 5g gap and which is used, and the saturation of the substance from which the core is made is completely undesirable.

However, in a third preferred embodiment of the invention, a gap 5g is introduced to create a characteristic which, for example, is shown in FIG. 1D. In this case, the gap 5g, as shown above, sets the equivalent inductance L _{equ of the} core, and this leads to the fact that it sets the saturation current Isat ∫ Vdt _sat / L _equ . Therefore, a third preferred embodiment of the present invention provides a very efficient way to implement saturable core blocks 5a, 5b and 5c, each of which has a linear characteristic.

FOURTH PREFERRED EMBODIMENT OF THE INVENTION

In the drawing of FIG. 4 is a circuit diagram showing a configuration of a high power inverter with forced switching according to a fourth preferred embodiment of the present invention.

In this preferred embodiment of the invention, each of the saturable core units 5a, 5b and 5c is implemented by parallel connection of the saturable inductor 51, 52 or 53 and the corresponding inductor 71, 72 or 73 of a linear electric reactor, where the saturable inductors 51, 52 and 53 are characterized the voltage integral over time at saturation is ∫Vdt _sat , and the linear electric reactors 71, 72 and 73 are characterized by the value of the equivalent inductance L _equ = ∫Vdt _sat / I _sat . It should be noted that the controller 94 functions similarly to the operation of the controller 93.

In the inverter according to the fourth preferred embodiment of the invention, the most preferred characteristics of each of the saturable core units 5a, 5b and 5c are achieved by the parallel connection of two separate devices. In this case, each device is specifically designed for one of the preferred characteristics of the voltage integral over time at saturation ∫Vdt _sat and equivalent inductance L _equ in the linear region. Thus, stable and low loss saturable core blocks 5a, 5b, and 5c are implemented. In other words, saturable inductors 51, 52 and 53 are selected in such a way that they have the smallest hysteresis loss, and the linear inductors 71, 72 and 73 are designed only for saturation current I _sat . The smallest hysteresis losses are usually achieved by using a saturable core having a steep and narrow magnetization curve, which in this case leads to a very low saturation current of the saturable core.

Unlike the linear anode electric reactor used in the inverter of the prior art, the linear inductor is designed only for saturation current I _sat . As a result, low hysteresis losses coupled with low conductivity lead to high inverter efficiency.

FIFTH PREFERRED EMBODIMENT OF THE INVENTION

In the drawings of FIG. 5A-FIG. 5E shows a high power, high power inverter according to a fifth preferred embodiment of the present invention. In the drawing of FIG. 5A is a circuit diagram illustrating a configuration of a saturable core unit 5a for use in a forced switching high power inverter according to a fifth preferred embodiment of the present invention. In this preferred embodiment of the invention shown in FIG. 5A, resistors 511 and 711 are included respectively in the circuit of the saturable inductor 51 and in the circuit of the linear inductor 71, and they are balanced according to the following equation:

(I _DC5a × R ₅₁₁ ) / R ₇₁₁ ≤I _sat / 2 and

preferably (I _DC5a × R ₅₁₁ ) / R ₇₁₁ ≤I _sat / 5

In the experiment of FIG. 5A, the following parameters were used:

(a) the voltage integral over time ∫Vdt = 2.4 millivolts × second for saturable inductor 51;

(b) the resistance of the resistor 511, R ₅₁₁ = 10 μOhm (microohm);

(c) the inductance of the linear inductor 71, L ₇₁ = L _equ = 25 μH;

(d) saturation output current I _sat = 96 A;

(e) direct current flowing in block 5a with a saturable core, I _DC5a = -1000 A and

(f) alternating current flowing in block 5a with a saturable core, I _AC5a = 3000 A _peak .

The following is an explanation of the effect of the balance of resistors 511 and 711 on the characteristics of the inverter with reference to the drawings of FIG. 5B-FIG. 5E, showing typical signals of a saturable core block 5a under load with a DC offset I _DC5a = 1000 A at time t ₁ . After that, the load is stopped to check the return of the core to its original state. In the drawings of FIG. 5B-FIG. 5E, the upper graph shows the current I _5a flowing in the saturable core block 5a, and the lower graph shows the current I ₇₁ flowing in the linear inductor 71, and also shows the normalized magnetic flux or the normalized magnetization of the saturated inductor 51.

In the drawing of FIG. 5B shows the first part of the signal timing diagram in the unbalanced case, which shows (a) the current I _5a of the saturated core unit 5a and (b) the current I _{71 of the} inductance 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A, and in the drawing of FIG. 5C shows the second part of the signal timing diagram in the unbalanced case, which shows (a) the current I _5a of the saturated core unit 5a and (b) the current I _{71 of the} inductance 71 of FIG. 5A, and the normalized magnetic flux F _{51 of the} saturable inductor 51 of FIG. 5A. In the drawings of FIG. 5B and FIG. 5C shows an unbalanced case in which R ₅₁₁ = R ₇₁₁ = 10 μOhm (microohm). As shown in FIG. 5B, when checking the reset, after a period of time t ₁ = 4 milliseconds, the core unit 5a behaves as follows. In this case, the core unit 5a returns to a mode having a saturation state ∫Vdt = 0 × ∫Vdt _sat . However, as shown in FIG. 5C, when checking the reset, after some time at time t ₁ = 199 milliseconds, the core unit 5a fails to return to the initial state as follows. In this case, the core unit 5a returns to the state ∫Vdt = -1 × ∫Vdt _sat .

In the drawing of FIG. 5D shows the first part of the signal timing diagram in the preferred case, showing (a) the current I _5a of the saturated core unit 5a and (b) the inductance current I _{71 of} 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A, and in the drawing of FIG. 5E depicts a second portion of the signal timing diagram in the preferred case, showing (a) the current I _5a of the saturable core unit 5a and (b) the inductance current I _{71 of} 71 of FIG. 5A and normalized magnetic flux F _{51 of} saturable inductor 51 of FIG. 5A. In the drawings of FIG. 5D and FIG. 5E shows a preferred case in which R ₅₁₁ = 10 μOhm and R ₇₁₁ = 1 mOhm (milliOhm). As shown in FIG. 5D, when checking the reset, after a period of time t ₁ = 4 milliseconds, the core block 5a behaves as follows. In this case, the core unit 5a returns to a mode having a saturation state ∫Vdt = 0 × ∫Vdt _sat . As shown in FIG. 5E, when checking the reset, after some time at a time t ₁ = 199 milliseconds, the core unit 5a still returns well to the initial state as follows. In this case, the core unit 5a returns to the state ∫Vdt = 0.07 × ∫Vdt _sat .

Finally, it is mentioned that a time dependence should be observed. From FIG. 5D it is also clear that the current flowing in the linear inductor 71 and in the resistor 711 of the inductor is determined by the integral of the voltage over the time that is supplied to them during each current transition of the saturated block 5a through zero. Then, the current flowing in the linear inductor 71 is kept constant, since the voltage on the saturated core unit 5a becomes small. In this case, the time constant of the resistive inductive circuit (RL circuit) of the components 71 and 711 should be large enough to hold the current, satisfying the following relationships:

τ _71-711> 2 × t _H, and τ _71-711> 2 × t _L,

where t _H and t _L denote the values of the time duration, respectively, of the positive and negative currents in block 5a with a saturated core. In addition, the time constant is determined by the values of the resistance R ₇₁₁ and inductance L ₇ as follows:

τ _71-711 = L ₇₁ / R ₇₁₁

In this case, make the following conclusion about the upper limit:

R ₇₁₁ <1/2 × L ₇₁ / t _H, and R ₇₁₁ <1/2 × L ₇₁ / t _L

Furthermore, even significantly higher current storage is preferred. Therefore, the following ratios are more preferred:

R ₇₁₁ <1/4 × L ₇₁ / t _H, and R ₇₁₁ <1/4 × L ₇₁ / t _L.

An inverter according to a fifth preferred embodiment of the invention can reliably correctly reset a saturated core unit 5a to its initial state.

SIXTH PREFERRED EMBODIMENT OF THE INVENTION

In the drawing of FIG. 6A is a circuit diagram illustrating a configuration of a high power, high power inverter according to a sixth preferred embodiment of the present invention. In particular, this preferred embodiment of the invention is focused on reverse recovery of the reverse diode 22 and reverse diode 24, which are shown in FIG. 6A, but with the same success can be applied to other configurations, such as, for example, a circuit breaker, a three-level inverter, etc. It should be noted that the controller 96 functions similarly to the operation of the controller 92.

High voltage reverse diodes 22 and 24 usually tend to become "instantaneous" if they are designed for high speed and low losses during reverse recovery. Instantaneous action appears at the end of the reverse recovery process. In this case, the extraction of all charge carriers occurs suddenly, and then the reverse recovery current drops to a current equal to zero. As a result of this, large surges and fluctuations of excess voltage are observed in them.

The nature of the instantaneous action strongly depends on the direct current flowing in each of the diodes 22 and 24. With a large forward current at a high load, each of the diodes 22 and 24 can usually have a relatively smooth behavior, but with a small forward current it is so instantaneous that it can be destroyed even at a relatively low slew rate dI / dt.

In the conventional circuit of the prior art, which is the circuit breaker of FIG. 1A without block 5a with a saturable core, the reverse recovery mode of each of the diodes 22 and 24 is fixed by the same slew rate dI / dt in the case of small and large forward current. Then, in the case of a small forward current, this leads to a relatively large reverse recovery current. In this case, the maximum of the reverse recovery current and the maximum of the reverse recovery voltage occur simultaneously in time. The aforementioned condition of timing in time is characteristic of a purely inductive load, and it is precisely it that is most needed for diodes 22 and 24.

Unlike the conventional chopper circuit, a high power, high-power inverter according to a second preferred embodiment of the present invention can cope with the difficult situation of reverse recovery in the case of low forward current much better, as already shown in FIG. 2J. Further improvement has been achieved through a sixth preferred embodiment of the present invention.

In the drawing of FIG. 6B is a signal timing diagram showing the voltage V _5a of the saturated core unit 5a of FIG. 6A, as well as voltage V ₂₂ and current I _{22 of the} reverse diode 22 of FIG. 6A, when the level locking circuit 3 comprises a clamping resistor 331 with a typical scattering inductance 331a of a clamping resistor of 1.5 μH (microgenry). The output current I _{out is} set to I _out = 100 A.

A forced-switched high power inverter according to a sixth preferred embodiment of the invention is particularly oriented to such a difficult reverse recovery situation in the case of a small forward current. The sixth preferred embodiment of the invention further comprises a clamp level reset circuit 33, which consists of a parallel connection circuit comprising the following circuits:

(a) a parallel connection circuit comprising a clamp resistor 331 and a leakage inductance 331a (or equivalent inductance) of a clamp resistor; and

(b) a low impedance resistive-capacitive circuit (RC) parallel circuit, which includes a pulse limiting resistor 333, a pulse capacitor 334, and a leakage inductance 334a.

The aforementioned resistive-capacitive (RC) circuit is designed in such a way that it makes the greatest contribution to the total current of the voltage level circuit 33 of the fixation level at the very beginning of the reception of the voltage change. This causes the capacitive circuit to increase the reverse recovery current of the diode at the very beginning, and later it adds damping to the leakage inductance 331a of the clamp resistor.

In the drawing of FIG. 6C is a signal timing chart showing the voltage V _5a of the saturated core unit 5a of FIG. 6A, as well as voltage V ₂₂ and current I _{22 of the} reverse diode 22 of FIG. 6A, when the reverse recovery current flowing through the diode is amplified immediately at the very beginning, and damping is added to the dissipation inductance of the fixing resistor 331a. As shown in FIG. 6C, the reverse recovery of the reverse diode 22 (or 24) has become extremely smooth and provided extremely good support for the diode 22 (or 24) during charge accumulation.

SEVENTY PREFERRED EMBODIMENT OF THE INVENTION

In the drawing of FIG. 7A is a circuit diagram illustrating a configuration of a high power forced-switching inverter according to a seventh preferred embodiment of the present invention. This preferred embodiment of the invention is aimed at reducing losses. It should be noted that the controller 97 functions similarly to the operation of the controller 92.

In the drawing of FIG. 7B is a timing diagram of signals in the case without any core 336 causing a delay, which shows the voltage V _5a of the saturated core block 5a, the voltage V _5b of the saturated core block 5b, the voltage V ₂₂ and the current I _{22 of the} reverse diode 22, and current I _{33 of the} clamp level reset circuit 33. In this case, the output current I _{out is} set to I _out = 3000 A.

From FIG. 7B, it is understood that at a high load current in the circuit 33, the voltage of the fixation level for a relatively long period of time (t ₁ -t ₂ ) a relatively large current flows without any effect on the reverse recovery of the corresponding reverse diodes 22 and 24. t ₁ -t ₂ ) is generated by the transition of block 5b with a saturable core from one state to another, which allows the device 21 of the lockable valve to be supplied with current from the level fixing circuit 3. The aforementioned electric current causes power dissipation in the clamp level reset circuit 33.

According to a seventh preferred embodiment of the invention, a delay core is additionally inserted into the line of the fixing resistor 331 and the leakage inductance 331a of the fixing resistor. The aforementioned delay causing core 336 may simply be another saturable core. However, the effective value of the current flowing in the core 336 causing the delay is much smaller than the current flowing in each of the saturable core blocks 5a, 5b and 5c. Therefore, the core 336 causing the delay can be made much smaller than the core of each of the saturated core blocks 5a, 5b and 5c.

In the drawing of FIG. 7C shows a timing diagram of signals in the case of a core 336 causing a delay, showing the voltage V _5a of the saturated core block 5a, the voltage V _5b of the saturated core block 5b, the voltage V ₂₂ and the current I _{22 of the} reverse diode 22, and the current I ₃₃ circuit 33 reset voltage level fixation. From the drawing of FIG. 7C, it is understood that the delay causing core 336 delays the current I ₃₃ flowing in the limiting resistor 331. As a result, a reduction in losses is achieved, especially with a large operating current.

SUITABILITY FOR INDUSTRIAL PURPOSES

As described in detail above, according to the aforementioned device of a high power inverter with forced switching, since the device of the inverter with forced switching, which has a built-in clearly defined initial state and forced action, use a block with a saturable core, a well-defined application can be realized functioning in almost any environment. As a result, reliable control of the reverse recovery current of the diode can be realized.

Claims (13)

1. The device is a high power inverter with forced switching, having a maximum rated output current I _Rout , comprising: at least one DC coupling capacitor having a voltage ripple characterized by a maximum value dV _{m of the} absolute value of the slew rate dV _DC / dt, which satisfies the relation dV _m ≤ dV _DC / dt≤dV _m ;
at least one anode dissipation inductance connected in series with the coupling capacitor for direct current;
at least one switch arm including a series connection of at least one lockable valve device and at least one reverse diode;
at least one level fixing circuit including at least one fixing capacitor, at least one fixing diode and at least one fixing level voltage reset circuit, which includes at least one resistor and at least one saturable core block,
wherein said at least one saturable core unit has one of a linear saturation characteristic and a smooth saturation characteristic, each of which has a saturation current equal to I _sat , and wherein a saturation current I _{sat is} set so that it is large than the bias current generated due to the slew rate dV _m , with capacitance C _{31 of} the at least one fixing capacitor, so that the ratio
I _Rout > I _sat > C ₃₁ × dV _m . 2. The high power inverter device with forced switching according to claim 1, in which the saturation current I _{sat is} set in such a way that satisfies the relation
I _Rout > I _sat > 4 × C ₃₁ × dV _m . 3. The device is a high power inverter with forced switching according to claim 1 or 2,
in which the saturation current I _{sat is} set in such a way that satisfies the relation
I _Rout / 5> I _sat > C ₃₁ × dV _m . 4. The high-power inverter device with forced switching according to claim 1 or 2, in which the saturation current I _{sat is} set in such a way that satisfies the relation
I _Rout / 5> I _sat > 4 × C ₃₁ × dV _m . 5. The device of the high power inverter with forced switching according to claim 1 or 2, in which the said at least one reverse diode has an anode electric reactor tuned to an allowable power P _rrlar (I) reverse recovery, causing harmful effects, which is determined using the adjusted linear electric anode reactors, wherein said at least one saturable core unit has an integral with respect to time of voltage saturation ∫Vdt _sat, wherein said high power inverter forced commutation generates power P _rr (I) reverse recovery causing harmful effects on the at least one freewheeling diode, wherein the time integral ∫Vdt _sat saturation voltage is selected such that Prr (I) ≤P _rrlar ( I) for the aforementioned diodes that are affected by the reverse recovery, which is caused by the inverter output current falling within the interval 0 <I _out ≤I _Rout , and in which the time saturation voltage integral ∫Vdt _{sat is} chosen so that P _rr (I) ≤1 / 2 × P _rrlar (I), according IU shey least one diode which is under the influence of the harmful reverse recovery diodes of said at least one current level of I _out, which is caused by the fact that the inverter output current is within the range 0 <I _out ≤I _Rout. 6. The device is a high power inverter with forced switching according to claim 1 or 2, in which the said at least one block with a saturable core contains at least one saturable inductor having at least one gap filled with non-magnetic substance, whereby the aforementioned at least one block with a saturable core has a saturation current I _sat . 7. The device of the high power inverter with forced switching according to claim 1 or 2, in which the said at least one block with a saturable core contains at least one saturable inductor and at least one linear inductor, which is connected parallel to said at least one saturable inductor, wherein said at least one saturable inductor is characterized by a time saturation voltage integral ∫Vdt _{sat of} said at least one saturable core block, and in which said at least one linear inductor has an inductance L ₇₁ = L _equ = ∫ Vdt _sat obtained from the integral of the saturation voltage over time ∫ Vdt _sat and the saturation current I _{sat of} said at least one saturable core block. 8. The device of the high-power inverter with forced switching according to claim 7, in which in said at least one block with a saturable core flows the maximum DC component I _DC5a , in which said at least one block with a saturable core contains at least one saturable core bus resistance R ₅₁₁ and at least one inductor resistance R ₇₁₁ , and wherein said at least one saturable core bus resistance R ₅₁₁ and said at least at least one inductor resistance R _{711 is} set in such a way that they satisfy the equations below, where t _H is the duration of the positive current and t _L is the duration of the negative current flowing in the saturable core block:
(I _DC5a × R ₅₁₁ ) / R ₇₁₁ ≤1 / 2 × I _sat and
R ₇₁₁ <1/2 × L ₇₁ / t _H and R ₇₁₁ <1/2 × L ₇₁ / t _L. 9. The high-power forced-switching inverter device of claim 8, wherein said at least one saturated core bus resistance R ₅₁₁ and said at least one inductor resistance R _{711 are} set in such a way that they satisfy the following equations:
(I _DC5a × R5 ₁₁ ) / R ₇₁₁ ≤1 / 2 × I _sat and
R ₇₁₁ <1/4 × L ₇₁ / t _H and R ₇₁₁ <1/4 × L ₇₁ / t _L. 10. The high-power forced-switching inverter device of claim 8, wherein said at least one saturated core bus resistance R ₅₁₁ and said at least one inductor resistance R _{711 are} set in such a way that they satisfy the following equations:
(I _DC5a × R ₅₁₁ ) / R ₇₁₁ ≤1 / 5 × I _sat and
R ₇₁₁ <1/2 × L ₇₁ / t _H and R ₇₁₁ <1/2 × L ₇₁ / t _L. 11. The forced-switching high-power inverter device of claim 8, wherein said at least one saturated core bus resistance R ₅₁₁ and said at least one inductor resistance R _{711 are} set in such a way that they satisfy the following equations:
(I _DC5a × R ₅₁₁ ) / R ₇₁₁ ≤1 / 5 × I _sat and
R ₇₁₁ <1/4 × L _7l / tH; and R ₇₁₁ <1/4 × L ₇₁ / t _L. 12. The device is a high power inverter with forced switching according to claim 1 or 2,
wherein said at least one fixation level voltage reset circuit further comprises at least one fixing resistor, at least one pulse capacitor and at least one pulse limiting resistor. 13. The device of the high power inverter with forced switching according to item 12, in which the aforementioned at least one circuit reset voltage level fixation additionally contains at least one core, causing a delay.

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