AU2002357739A1 - Viterbi convolutional coding method and apparatus - Google Patents
Viterbi convolutional coding method and apparatusInfo
- Publication number
- AU2002357739A1 AU2002357739A1 AU2002357739A AU2002357739A AU2002357739A1 AU 2002357739 A1 AU2002357739 A1 AU 2002357739A1 AU 2002357739 A AU2002357739 A AU 2002357739A AU 2002357739 A AU2002357739 A AU 2002357739A AU 2002357739 A1 AU2002357739 A1 AU 2002357739A1
- Authority
- AU
- Australia
- Prior art keywords
- coding method
- convolutional coding
- viterbi convolutional
- viterbi
- convolutional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/413—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors tail biting Viterbi decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
- H03M13/4192—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using combined traceback and register-exchange
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/6583—Normalization other than scaling, e.g. by subtraction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6577—Representation or format of variables, register sizes or word-lengths and quantization
- H03M13/6583—Normalization other than scaling, e.g. by subtraction
- H03M13/6586—Modulo/modular normalization, e.g. 2's complement modulo implementations
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33239801P | 2001-11-16 | 2001-11-16 | |
US60/332,398 | 2001-11-16 | ||
PCT/US2002/036998 WO2003044962A2 (en) | 2001-11-16 | 2002-11-15 | Viterbi convolutional coding method and apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
AU2002357739A1 true AU2002357739A1 (en) | 2003-06-10 |
AU2002357739A8 AU2002357739A8 (en) | 2003-06-10 |
Family
ID=23298053
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2002357739A Abandoned AU2002357739A1 (en) | 2001-11-16 | 2002-11-15 | Viterbi convolutional coding method and apparatus |
Country Status (3)
Country | Link |
---|---|
US (1) | US20030123579A1 (US20030123579A1-20030703-M00002.png) |
AU (1) | AU2002357739A1 (US20030123579A1-20030703-M00002.png) |
WO (1) | WO2003044962A2 (US20030123579A1-20030703-M00002.png) |
Families Citing this family (38)
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US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
DE19651075A1 (de) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen |
DE19654595A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen |
DE59710317D1 (de) | 1996-12-27 | 2003-07-24 | Pact Inf Tech Gmbh | VERFAHREN ZUM SELBSTÄNDIGEN DYNAMISCHEN UMLADEN VON DATENFLUSSPROZESSOREN (DFPs) SOWIE BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN (FPGAs, DPGAs, o.dgl.) |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (de) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Verfahren zur Reparatur von integrierten Schaltkreisen |
US7003660B2 (en) | 2000-06-13 | 2006-02-21 | Pact Xpp Technologies Ag | Pipeline configuration unit protocols and communication |
AU5805300A (en) | 1999-06-10 | 2001-01-02 | Pact Informationstechnologie Gmbh | Sequence partitioning in cell structures |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
DE60117421T2 (de) * | 2000-11-15 | 2006-09-07 | Texas Instruments Inc., Dallas | Vollen Pfadmetrikrechner in Viterbidekodierung |
US7210129B2 (en) * | 2001-08-16 | 2007-04-24 | Pact Xpp Technologies Ag | Method for translating programs for reconfigurable architectures |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
JP2004533691A (ja) * | 2001-06-20 | 2004-11-04 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | データを処理するための方法 |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
WO2003060747A2 (de) | 2002-01-19 | 2003-07-24 | Pact Xpp Technologies Ag | Reconfigurierbarer prozessor |
AU2003214003A1 (en) | 2002-02-18 | 2003-09-09 | Pact Xpp Technologies Ag | Bus systems and method for reconfiguration |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
WO2004021176A2 (de) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Verfahren und vorrichtung zur datenverarbeitung |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
AU2003289844A1 (en) | 2002-09-06 | 2004-05-13 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
US7260154B1 (en) * | 2002-12-30 | 2007-08-21 | Altera Corporation | Method and apparatus for implementing a multiple constraint length Viterbi decoder |
EP1676208A2 (en) | 2003-08-28 | 2006-07-05 | PACT XPP Technologies AG | Data processing device and method |
US7343530B2 (en) * | 2004-02-10 | 2008-03-11 | Samsung Electronics Co., Ltd. | Turbo decoder and turbo interleaver |
KR20070007119A (ko) * | 2004-04-05 | 2007-01-12 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 4개의 심벌의 병렬 비터비 디코더 |
US8111617B2 (en) * | 2004-08-13 | 2012-02-07 | Broadcom Corporation | Multiple independent pathway communications |
KR100725931B1 (ko) * | 2004-12-17 | 2007-06-11 | 한국전자통신연구원 | 하이브리드 역추적 장치 및 그를 이용한 고속 비터비 복호시스템 |
US7441174B2 (en) * | 2005-09-07 | 2008-10-21 | The University Of Hong Kong | Embedded state metric storage for MAP decoder of turbo codes |
JP2009524134A (ja) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | ハードウェア定義方法 |
US8755515B1 (en) | 2008-09-29 | 2014-06-17 | Wai Wu | Parallel signal processing system and method |
US8638886B2 (en) * | 2009-09-24 | 2014-01-28 | Credo Semiconductor (Hong Kong) Limited | Parallel viterbi decoder with end-state information passing |
US10075186B2 (en) | 2015-11-18 | 2018-09-11 | Cisco Technology, Inc. | Trellis segment separation for low-complexity viterbi decoding of high-rate convolutional codes |
US9935800B1 (en) | 2016-10-04 | 2018-04-03 | Credo Technology Group Limited | Reduced complexity precomputation for decision feedback equalizer |
US10728059B1 (en) | 2019-07-01 | 2020-07-28 | Credo Technology Group Limited | Parallel mixed-signal equalization for high-speed serial link |
Family Cites Families (20)
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US4730322A (en) * | 1985-09-27 | 1988-03-08 | California Institute Of Technology | Method and apparatus for implementing a maximum-likelihood decoder in a hypercube network |
JPS62233933A (ja) * | 1986-04-03 | 1987-10-14 | Toshiba Corp | ヴイタビ復号法 |
US5105387A (en) * | 1989-10-13 | 1992-04-14 | Texas Instruments Incorporated | Three transistor dual port dynamic random access memory gain cell |
KR940010435B1 (ko) * | 1992-08-31 | 1994-10-22 | 삼성전자 주식회사 | 비터비 복호기의 경로기억장치 |
US5490178A (en) * | 1993-11-16 | 1996-02-06 | At&T Corp. | Power and time saving initial tracebacks |
US5781756A (en) * | 1994-04-01 | 1998-07-14 | Xilinx, Inc. | Programmable logic device with partially configurable memory cells and a method for configuration |
FR2724273B1 (fr) * | 1994-09-05 | 1997-01-03 | Sgs Thomson Microelectronics | Circuit de traitement de signal pour mettre en oeuvre un algorithme de viterbi |
US5586128A (en) * | 1994-11-17 | 1996-12-17 | Ericsson Ge Mobile Communications Inc. | System for decoding digital data using a variable decision depth |
FI100564B (fi) * | 1995-12-04 | 1997-12-31 | Nokia Telecommunications Oy | Menetelmä transitiometriikan muodostamiseksi ja solukkoradiojärjestelm än vastaanotin |
US5841478A (en) * | 1996-04-09 | 1998-11-24 | Thomson Multimedia, S.A. | Code sequence detection in a trellis decoder |
US5878098A (en) * | 1996-06-27 | 1999-03-02 | Motorola, Inc. | Method and apparatus for rate determination in a communication system |
JP3266182B2 (ja) * | 1997-06-10 | 2002-03-18 | 日本電気株式会社 | ビタビ復号器 |
JP3277856B2 (ja) * | 1997-08-29 | 2002-04-22 | 日本電気株式会社 | ビタビデコーダ |
US6456628B1 (en) * | 1998-04-17 | 2002-09-24 | Intelect Communications, Inc. | DSP intercommunication network |
US6269129B1 (en) * | 1998-04-24 | 2001-07-31 | Lsi Logic Corporation | 64/256 quadrature amplitude modulation trellis coded modulation decoder |
US7020214B2 (en) * | 2000-09-18 | 2006-03-28 | Lucent Technologies Inc. | Method and apparatus for path metric processing in telecommunications systems |
CN1212010C (zh) * | 2000-10-17 | 2005-07-20 | 皇家菲利浦电子有限公司 | 多标准信道解码器以及信道解码方法 |
DE60117421T2 (de) * | 2000-11-15 | 2006-09-07 | Texas Instruments Inc., Dallas | Vollen Pfadmetrikrechner in Viterbidekodierung |
KR20030005768A (ko) * | 2001-07-10 | 2003-01-23 | 삼성전자 주식회사 | 비터비 디코더의 상태 메트릭 연산 장치 |
US20030081569A1 (en) * | 2001-10-25 | 2003-05-01 | Nokia Corporation | Method and apparatus providing call admission that favors mullti-slot mobile stations at cell edges |
-
2002
- 2002-11-15 US US10/298,249 patent/US20030123579A1/en not_active Abandoned
- 2002-11-15 AU AU2002357739A patent/AU2002357739A1/en not_active Abandoned
- 2002-11-15 WO PCT/US2002/036998 patent/WO2003044962A2/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US20030123579A1 (en) | 2003-07-03 |
AU2002357739A8 (en) | 2003-06-10 |
WO2003044962A3 (en) | 2003-10-30 |
WO2003044962A2 (en) | 2003-05-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |