AU2002250505A1 - Beol process for cu metallizations free from al-wirebond pads - Google Patents

Beol process for cu metallizations free from al-wirebond pads

Info

Publication number
AU2002250505A1
AU2002250505A1 AU2002250505A AU2002250505A AU2002250505A1 AU 2002250505 A1 AU2002250505 A1 AU 2002250505A1 AU 2002250505 A AU2002250505 A AU 2002250505A AU 2002250505 A AU2002250505 A AU 2002250505A AU 2002250505 A1 AU2002250505 A1 AU 2002250505A1
Authority
AU
Australia
Prior art keywords
metallizations
free
beol process
wirebond pads
wirebond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002250505A
Other languages
English (en)
Inventor
Hans-Joachim Barth
Petra Felsner
Gerald Friese
Erdem Kaltalioglu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of AU2002250505A1 publication Critical patent/AU2002250505A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
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AU2002250505A 2002-04-02 2002-04-02 Beol process for cu metallizations free from al-wirebond pads Abandoned AU2002250505A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/010409 WO2003085735A1 (en) 2002-04-02 2002-04-02 Beol process for cu metallizations free from al-wirebond pads

Publications (1)

Publication Number Publication Date
AU2002250505A1 true AU2002250505A1 (en) 2003-10-20

Family

ID=28789618

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002250505A Abandoned AU2002250505A1 (en) 2002-04-02 2002-04-02 Beol process for cu metallizations free from al-wirebond pads

Country Status (4)

Country Link
EP (1) EP1490906A1 (de)
JP (1) JP2005522055A (de)
AU (1) AU2002250505A1 (de)
WO (1) WO2003085735A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004061307B4 (de) * 2004-12-20 2008-06-26 Infineon Technologies Ag Halbleiterbauteil mit Passivierungsschicht
JP5060100B2 (ja) 2006-10-26 2012-10-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7829450B2 (en) 2007-11-07 2010-11-09 Infineon Technologies Ag Method of processing a contact pad, method of manufacturing a contact pad, and integrated circuit element
US10957642B1 (en) 2019-09-20 2021-03-23 International Business Machines Corporation Resistance tunable fuse structure formed by embedded thin metal layers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005472A (en) * 1975-05-19 1977-01-25 National Semiconductor Corporation Method for gold plating of metallic layers on semiconductive devices
JPS6010796A (ja) * 1983-06-30 1985-01-19 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 配線構造体
US5731624A (en) * 1996-06-28 1998-03-24 International Business Machines Corporation Integrated pad and fuse structure for planar copper metallurgy
US6794752B2 (en) * 1998-06-05 2004-09-21 United Microelectronics Corp. Bonding pad structure
US6069066A (en) * 1998-12-09 2000-05-30 United Microelectronics Corp. Method of forming bonding pad
US6071808A (en) * 1999-06-23 2000-06-06 Lucent Technologies Inc. Method of passivating copper interconnects in a semiconductor
US6455913B2 (en) * 2000-01-31 2002-09-24 United Microelectronics Corp. Copper fuse for integrated circuit
US6730982B2 (en) * 2001-03-30 2004-05-04 Infineon Technologies Ag FBEOL process for Cu metallizations free from Al-wirebond pads

Also Published As

Publication number Publication date
JP2005522055A (ja) 2005-07-21
WO2003085735A1 (en) 2003-10-16
EP1490906A1 (de) 2004-12-29

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