AU2002239383A1 - Low defect density, thin-layer, soi substrates - Google Patents

Low defect density, thin-layer, soi substrates

Info

Publication number
AU2002239383A1
AU2002239383A1 AU2002239383A AU3938302A AU2002239383A1 AU 2002239383 A1 AU2002239383 A1 AU 2002239383A1 AU 2002239383 A AU2002239383 A AU 2002239383A AU 3938302 A AU3938302 A AU 3938302A AU 2002239383 A1 AU2002239383 A1 AU 2002239383A1
Authority
AU
Australia
Prior art keywords
thin
layer
defect density
low defect
soi substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002239383A
Other languages
English (en)
Inventor
Maria J. Anc
Robert P. Donald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibis Technology Corp
Original Assignee
Ibis Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibis Technology Corp filed Critical Ibis Technology Corp
Publication of AU2002239383A1 publication Critical patent/AU2002239383A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
AU2002239383A 2000-11-28 2001-11-28 Low defect density, thin-layer, soi substrates Abandoned AU2002239383A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/723,801 2000-11-28
US09/723,801 US6593173B1 (en) 2000-11-28 2000-11-28 Low defect density, thin-layer, SOI substrates
PCT/US2001/044689 WO2002045132A2 (fr) 2000-11-28 2001-11-28 Substrats de silicium sur isolant a couche mince et a faible densite de defauts

Publications (1)

Publication Number Publication Date
AU2002239383A1 true AU2002239383A1 (en) 2002-06-11

Family

ID=24907745

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002239383A Abandoned AU2002239383A1 (en) 2000-11-28 2001-11-28 Low defect density, thin-layer, soi substrates

Country Status (3)

Country Link
US (1) US6593173B1 (fr)
AU (1) AU2002239383A1 (fr)
WO (1) WO2002045132A2 (fr)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7223676B2 (en) * 2002-06-05 2007-05-29 Applied Materials, Inc. Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer
US7166524B2 (en) * 2000-08-11 2007-01-23 Applied Materials, Inc. Method for ion implanting insulator material to reduce dielectric constant
US6939434B2 (en) * 2000-08-11 2005-09-06 Applied Materials, Inc. Externally excited torroidal plasma source with magnetic control of ion distribution
US7294563B2 (en) * 2000-08-10 2007-11-13 Applied Materials, Inc. Semiconductor on insulator vertical transistor fabrication and doping process
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
US7288491B2 (en) * 2000-08-11 2007-10-30 Applied Materials, Inc. Plasma immersion ion implantation process
US7303982B2 (en) * 2000-08-11 2007-12-04 Applied Materials, Inc. Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage
US7137354B2 (en) * 2000-08-11 2006-11-21 Applied Materials, Inc. Plasma immersion ion implantation apparatus including a plasma source having low dissociation and low minimum plasma voltage
US7320734B2 (en) * 2000-08-11 2008-01-22 Applied Materials, Inc. Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage
US7037813B2 (en) * 2000-08-11 2006-05-02 Applied Materials, Inc. Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage
US7094316B1 (en) 2000-08-11 2006-08-22 Applied Materials, Inc. Externally excited torroidal plasma source
US7430984B2 (en) * 2000-08-11 2008-10-07 Applied Materials, Inc. Method to drive spatially separate resonant structure with spatially distinct plasma secondaries using a single generator and switching elements
JP2004152962A (ja) * 2002-10-30 2004-05-27 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7112509B2 (en) * 2003-05-09 2006-09-26 Ibis Technology Corporation Method of producing a high resistivity SIMOX silicon substrate
US7361570B1 (en) * 2003-09-17 2008-04-22 Texas Instruments Incorporated Semiconductor device having an implanted precipitate region and a method of manufacture therefor
JP2007529108A (ja) * 2003-10-24 2007-10-18 ソニー株式会社 半導体基板の製造方法及び半導体基板
US6949420B1 (en) * 2004-03-12 2005-09-27 Sony Corporation Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same
US7695590B2 (en) 2004-03-26 2010-04-13 Applied Materials, Inc. Chemical vapor deposition plasma reactor having plural ion shower grids
US7767561B2 (en) 2004-07-20 2010-08-03 Applied Materials, Inc. Plasma immersion ion implantation reactor having an ion shower grid
US8058156B2 (en) 2004-07-20 2011-11-15 Applied Materials, Inc. Plasma immersion ion implantation reactor having multiple ion shower grids
US7666464B2 (en) * 2004-10-23 2010-02-23 Applied Materials, Inc. RF measurement feedback control and diagnostics for a plasma immersion ion implantation reactor
US7476594B2 (en) * 2005-03-30 2009-01-13 Cree, Inc. Methods of fabricating silicon nitride regions in silicon carbide and resulting structures
US7428915B2 (en) * 2005-04-26 2008-09-30 Applied Materials, Inc. O-ringless tandem throttle valve for a plasma reactor chamber
US7312162B2 (en) * 2005-05-17 2007-12-25 Applied Materials, Inc. Low temperature plasma deposition process for carbon layer deposition
US7422775B2 (en) * 2005-05-17 2008-09-09 Applied Materials, Inc. Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing
US7335611B2 (en) * 2005-08-08 2008-02-26 Applied Materials, Inc. Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer
US7323401B2 (en) * 2005-08-08 2008-01-29 Applied Materials, Inc. Semiconductor substrate process using a low temperature deposited carbon-containing hard mask
US7429532B2 (en) * 2005-08-08 2008-09-30 Applied Materials, Inc. Semiconductor substrate process using an optically writable carbon-containing mask
US7312148B2 (en) * 2005-08-08 2007-12-25 Applied Materials, Inc. Copper barrier reflow process employing high speed optical annealing
US8450193B2 (en) * 2006-08-15 2013-05-28 Varian Semiconductor Equipment Associates, Inc. Techniques for temperature-controlled ion implantation
WO2008089168A2 (fr) * 2007-01-19 2008-07-24 Applied Materials, Inc. Chambre d'immersion en plasma
US8378384B2 (en) * 2007-09-28 2013-02-19 Infineon Technologies Ag Wafer and method for producing a wafer
US7879699B2 (en) * 2007-09-28 2011-02-01 Infineon Technologies Ag Wafer and a method for manufacturing a wafer
US8703516B2 (en) * 2008-07-15 2014-04-22 Infineon Technologies Ag MEMS substrates, devices, and methods of manufacture thereof
JPWO2011118205A1 (ja) * 2010-03-26 2013-07-04 株式会社Sumco Ｓｏｉウェーハの製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4676841A (en) 1985-09-27 1987-06-30 American Telephone And Telegraph Company, At&T Bell Laboratories Fabrication of dielectrically isolated devices utilizing buried oxygen implant and subsequent heat treatment at temperatures above 1300° C.
FR2616590B1 (fr) 1987-06-15 1990-03-02 Commissariat Energie Atomique Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche
JP2752799B2 (ja) 1991-03-27 1998-05-18 三菱マテリアル株式会社 Ｓｏｉ基板の製造方法
US5441899A (en) 1992-02-18 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator
IT1255764B (it) 1992-05-15 1995-11-15 Enichem Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici.
US5429955A (en) 1992-10-26 1995-07-04 Texas Instruments Incorporated Method for constructing semiconductor-on-insulator
US5661044A (en) 1993-11-24 1997-08-26 Lockheed Martin Energy Systems, Inc. Processing method for forming dislocation-free SOI and other materials for semiconductor use
US5989981A (en) * 1996-07-05 1999-11-23 Nippon Telegraph And Telephone Corporation Method of manufacturing SOI substrate
JPH1079355A (ja) 1996-09-03 1998-03-24 Komatsu Denshi Kinzoku Kk Ｓｏｉ基板の製造方法
US6043166A (en) 1996-12-03 2000-03-28 International Business Machines Corporation Silicon-on-insulator substrates using low dose implantation
US5930643A (en) 1997-12-22 1999-07-27 International Business Machines Corporation Defect induced buried oxide (DIBOX) for throughput SOI
JP3211233B2 (ja) * 1998-08-31 2001-09-25 日本電気株式会社 Ｓｏｉ基板及びその製造方法
CN1295733C (zh) 1999-12-14 2007-01-17 松下电器产业株式会社 高精细和高亮度ac型等离子体显示面板及其驱动方法
US6417078B1 (en) 2000-05-03 2002-07-09 Ibis Technology Corporation Implantation process using sub-stoichiometric, oxygen doses at different energies

Also Published As

Publication number Publication date
US6593173B1 (en) 2003-07-15
WO2002045132A9 (fr) 2004-04-29
WO2002045132A3 (fr) 2003-02-13
WO2002045132A2 (fr) 2002-06-06

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