AU2002236936A1 - High-density flip-chip interconnect - Google Patents

High-density flip-chip interconnect

Info

Publication number
AU2002236936A1
AU2002236936A1 AU2002236936A AU2002236936A AU2002236936A1 AU 2002236936 A1 AU2002236936 A1 AU 2002236936A1 AU 2002236936 A AU2002236936 A AU 2002236936A AU 2002236936 A AU2002236936 A AU 2002236936A AU 2002236936 A1 AU2002236936 A1 AU 2002236936A1
Authority
AU
Australia
Prior art keywords
chip interconnect
density flip
flip
density
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002236936A
Other languages
English (en)
Inventor
Mark P. Jamieson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2002236936A1 publication Critical patent/AU2002236936A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
AU2002236936A 2001-02-20 2002-02-01 High-density flip-chip interconnect Abandoned AU2002236936A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/789,401 2001-02-20
US09/789,401 US8125087B2 (en) 2001-02-20 2001-02-20 High-density flip-chip interconnect
PCT/US2002/002836 WO2002067325A2 (en) 2001-02-20 2002-02-01 High-density flip-chip interconnect

Publications (1)

Publication Number Publication Date
AU2002236936A1 true AU2002236936A1 (en) 2002-09-04

Family

ID=25147535

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002236936A Abandoned AU2002236936A1 (en) 2001-02-20 2002-02-01 High-density flip-chip interconnect

Country Status (7)

Country Link
US (1) US8125087B2 (https=)
EP (1) EP1364403A2 (https=)
JP (1) JP4156927B2 (https=)
KR (1) KR100732123B1 (https=)
CN (1) CN1331222C (https=)
AU (1) AU2002236936A1 (https=)
WO (1) WO2002067325A2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615606B1 (ko) * 2005-03-15 2006-08-25 삼성전자주식회사 메모리 모듈 및 이 모듈의 신호 라인 배치 방법
JP2009175198A (ja) 2008-01-21 2009-08-06 Sony Corp Ｅｌ表示パネル及び電子機器
US12033903B1 (en) * 2021-12-09 2024-07-09 Amazon Technologies, Inc. High-density microbump and probe pad arrangement for semiconductor components

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563029A (ja) * 1991-09-02 1993-03-12 Fujitsu Ltd 半導体素子
JPH05129366A (ja) * 1991-11-08 1993-05-25 Fujitsu Ltd 集積回路用ｔａｂ実装構造
US5545923A (en) * 1993-10-22 1996-08-13 Lsi Logic Corporation Semiconductor device assembly with minimized bond finger connections
US5424492A (en) * 1994-01-06 1995-06-13 Dell Usa, L.P. Optimal PCB routing methodology for high I/O density interconnect devices
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5764489A (en) * 1996-07-18 1998-06-09 Compaq Computer Corporation Apparatus for controlling the impedance of high speed signals on a printed circuit board
US5812379A (en) * 1996-08-13 1998-09-22 Intel Corporation Small diameter ball grid array pad size for improved motherboard routing
JPH10303562A (ja) * 1997-04-30 1998-11-13 Toshiba Corp プリント配線板
JP3386977B2 (ja) * 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
JP3152180B2 (ja) * 1997-10-03 2001-04-03 日本電気株式会社 半導体装置及びその製造方法
US6011695A (en) * 1998-11-02 2000-01-04 Intel Corporation External bus interface printed circuit board routing for a ball grid array integrated circuit package
US6310398B1 (en) * 1998-12-03 2001-10-30 Walter M. Katz Routable high-density interfaces for integrated circuit devices
DE60039569D1 (de) 1999-11-02 2008-09-04 Canon Kk Gedruckte Leiterplatte

Also Published As

Publication number Publication date
CN1568544A (zh) 2005-01-19
KR20040014460A (ko) 2004-02-14
KR100732123B1 (ko) 2007-06-25
US8125087B2 (en) 2012-02-28
WO2002067325A3 (en) 2003-05-30
JP2005505910A (ja) 2005-02-24
WO2002067325A2 (en) 2002-08-29
JP4156927B2 (ja) 2008-09-24
US20020113307A1 (en) 2002-08-22
CN1331222C (zh) 2007-08-08
EP1364403A2 (en) 2003-11-26

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase