AU2002225705A1 - Sequencer method of selectively inhibiting clock signals in a re-programmable i/o interface - Google Patents

Sequencer method of selectively inhibiting clock signals in a re-programmable i/o interface

Info

Publication number
AU2002225705A1
AU2002225705A1 AU2002225705A AU2570502A AU2002225705A1 AU 2002225705 A1 AU2002225705 A1 AU 2002225705A1 AU 2002225705 A AU2002225705 A AU 2002225705A AU 2570502 A AU2570502 A AU 2570502A AU 2002225705 A1 AU2002225705 A1 AU 2002225705A1
Authority
AU
Australia
Prior art keywords
programmable
interface
clock signals
selectively inhibiting
sequencer method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002225705A
Inventor
Michael A. Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intersil Americas LLC
Original Assignee
Intersil Americas LLC
Intersil Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Americas LLC, Intersil Inc filed Critical Intersil Americas LLC
Publication of AU2002225705A1 publication Critical patent/AU2002225705A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30069—Instruction skipping instructions, e.g. SKIP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
AU2002225705A 2000-11-20 2001-11-13 Sequencer method of selectively inhibiting clock signals in a re-programmable i/o interface Abandoned AU2002225705A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/717,495 2000-11-20
US09/717,495 US6871292B1 (en) 2000-11-20 2000-11-20 Sequencer and method of selectively inhibiting clock signals to execute reduced instruction sequences in a re-programmable I/O interface
PCT/US2001/043811 WO2002042919A2 (en) 2000-11-20 2001-11-13 Sequencer method of selectively inhibiting clock signals in a re-programmable i/o interface

Publications (1)

Publication Number Publication Date
AU2002225705A1 true AU2002225705A1 (en) 2002-06-03

Family

ID=24882248

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002225705A Abandoned AU2002225705A1 (en) 2000-11-20 2001-11-13 Sequencer method of selectively inhibiting clock signals in a re-programmable i/o interface

Country Status (3)

Country Link
US (1) US6871292B1 (en)
AU (1) AU2002225705A1 (en)
WO (1) WO2002042919A2 (en)

Families Citing this family (10)

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Publication number Priority date Publication date Assignee Title
JP4170218B2 (en) 2001-08-29 2008-10-22 メディアテック インコーポレーテッド Method and apparatus for improving the throughput of a cache-based embedded processor by switching tasks in response to a cache miss
US7058149B2 (en) * 2001-12-14 2006-06-06 Freescale Semiconductor, Inc. System for providing a calibrated clock and methods thereof
US7237216B2 (en) * 2003-02-21 2007-06-26 Infineon Technologies Ag Clock gating approach to accommodate infrequent additional processing latencies
DE10313112B4 (en) * 2003-03-24 2007-05-03 Fritz Egger Gmbh & Co. Covering with a plurality of panels, in particular floor covering, and method for laying panels
US7533106B2 (en) * 2005-09-09 2009-05-12 Quickfilter Technologies, Inc. Data structures and circuit for multi-channel data transfers using a serial peripheral interface
TWI324317B (en) * 2006-10-05 2010-05-01 Mstar Semiconductor Inc Apparatus and method for updating the function of a monitor
US20080181393A1 (en) * 2007-01-26 2008-07-31 Ronald Brost Methods and apparatus to maintain communication services during a power failure
US9280344B2 (en) * 2012-09-27 2016-03-08 Texas Instruments Incorporated Repeated execution of instruction with field indicating trigger event, additional instruction, or trigger signal destination
KR101456028B1 (en) * 2013-07-31 2014-11-03 주식회사 유니테스트 Apparatus for proofreading output signal using fpga of memory test device and method therefor
US11526641B2 (en) * 2020-08-25 2022-12-13 Synopsys, Inc. Formal gated clock conversion for field programmable gate array (FPGA) synthesis

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623017A (en) * 1969-10-22 1971-11-23 Sperry Rand Corp Dual clocking arrangement for a digital computer
US4379328A (en) 1979-06-27 1983-04-05 Burroughs Corporation Linear sequencing microprocessor facilitating
JP2569514B2 (en) * 1986-12-12 1997-01-08 株式会社日立製作所 Information processing device
JPH0276056A (en) 1988-09-13 1990-03-15 Toshiba Corp Information processor
JPH0387909A (en) * 1989-05-10 1991-04-12 Seiko Epson Corp Information processor and microprocessor
US5666522A (en) * 1994-01-28 1997-09-09 Micron Electronics, Inc. Variable speed controller
US5832257A (en) * 1995-12-29 1998-11-03 Atmel Corporation Digital signal processing method and system employing separate program and data memories to store data
JPH10162600A (en) * 1996-11-26 1998-06-19 Mitsubishi Electric Corp Semiconductor storage device having built-in testing function
US5958044A (en) 1997-01-24 1999-09-28 Texas Instruments Incorporated Multicycle NOP
JP3568539B2 (en) 1997-02-27 2004-09-22 三菱電機株式会社 Data processing device
US6504854B1 (en) * 1998-04-10 2003-01-07 International Business Machines Corporation Multiple frequency communications
US6522982B1 (en) * 1999-09-24 2003-02-18 Cirrus Logic, Inc. Energy-to-pulse converter systems, devices, and methods wherein the output frequency is greater than the calculation frequency and having output phasing

Also Published As

Publication number Publication date
US6871292B1 (en) 2005-03-22
WO2002042919A2 (en) 2002-05-30
WO2002042919A3 (en) 2002-09-06

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