AU5436200A - An arrangement and a method relating to design of circuits - Google Patents

An arrangement and a method relating to design of circuits

Info

Publication number
AU5436200A
AU5436200A AU54362/00A AU5436200A AU5436200A AU 5436200 A AU5436200 A AU 5436200A AU 54362/00 A AU54362/00 A AU 54362/00A AU 5436200 A AU5436200 A AU 5436200A AU 5436200 A AU5436200 A AU 5436200A
Authority
AU
Australia
Prior art keywords
circuits
arrangement
design
method relating
relating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU54362/00A
Inventor
Per Ingelhag
Klas Moreau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU5436200A publication Critical patent/AU5436200A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU54362/00A 1999-06-04 2000-06-02 An arrangement and a method relating to design of circuits Abandoned AU5436200A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9902079 1999-06-04
SE9902079A SE516166C2 (en) 1999-06-04 1999-06-04 An apparatus and method relating to timing of circuits
PCT/SE2000/001146 WO2000075815A1 (en) 1999-06-04 2000-06-02 An arrangement and a method relating to design of circuits

Publications (1)

Publication Number Publication Date
AU5436200A true AU5436200A (en) 2000-12-28

Family

ID=20415907

Family Applications (1)

Application Number Title Priority Date Filing Date
AU54362/00A Abandoned AU5436200A (en) 1999-06-04 2000-06-02 An arrangement and a method relating to design of circuits

Country Status (3)

Country Link
AU (1) AU5436200A (en)
SE (1) SE516166C2 (en)
WO (1) WO2000075815A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1308862B1 (en) * 2001-10-29 2009-07-15 Telefonaktiebolaget LM Ericsson (publ) Optimization of the design of a synchronous digital circuit
US7302657B2 (en) 2001-10-29 2007-11-27 Telefonaktiebolaget L M Ericsson (Publ) Optimization of the design of a synchronous digital circuit
US6647540B2 (en) * 2001-11-08 2003-11-11 Telefonaktiebolaget Lm Ericsson(Publ) Method for reducing EMI and IR-drop in digital synchronous circuits
US8065646B2 (en) 2005-09-07 2011-11-22 Freescale Semiconductor, Inc. Method and a computer readable medium for performing static timing analysis of a design of an integrated circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455931A (en) * 1993-11-19 1995-10-03 International Business Machines Corporation Programmable clock tuning system and method
US5507029A (en) * 1995-01-11 1996-04-09 International Business Machines Corporation Method for minimizing the time skew of electrical signals in very large scale integrated circuits
US5778216A (en) * 1995-06-30 1998-07-07 Cadence Design Systems, Inc. Method for hierarchical time drive circuit layout by rebudgeting timing constraints of plurality of logical blocks after placement
US5724250A (en) * 1996-02-07 1998-03-03 Unisys Corporation Method and apparatus for performing drive strength adjust optimization in a circuit design
JPH1063703A (en) * 1996-08-26 1998-03-06 Toshiba Corp Method for designing low power consumption circuit

Also Published As

Publication number Publication date
SE9902079L (en) 2000-12-05
WO2000075815A1 (en) 2000-12-14
SE9902079D0 (en) 1999-06-04
SE516166C2 (en) 2001-11-26

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase