AU2002212702A1 - Parallel operation device, entertainment device, operating method, computer program, and semiconductor device - Google Patents

Parallel operation device, entertainment device, operating method, computer program, and semiconductor device

Info

Publication number
AU2002212702A1
AU2002212702A1 AU2002212702A AU1270202A AU2002212702A1 AU 2002212702 A1 AU2002212702 A1 AU 2002212702A1 AU 2002212702 A AU2002212702 A AU 2002212702A AU 1270202 A AU1270202 A AU 1270202A AU 2002212702 A1 AU2002212702 A1 AU 2002212702A1
Authority
AU
Australia
Prior art keywords
computer program
operating method
parallel operation
entertainment
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002212702A
Inventor
Hidetaka Magoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Publication of AU2002212702A1 publication Critical patent/AU2002212702A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4814—Non-logic devices, e.g. operational amplifiers
AU2002212702A 2000-11-02 2001-11-02 Parallel operation device, entertainment device, operating method, computer program, and semiconductor device Abandoned AU2002212702A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2000-335787 2000-11-02
JP2000335787 2000-11-02
JP2001318590A JP3338043B2 (en) 2000-11-02 2001-10-16 Parallel arithmetic device, entertainment device, arithmetic processing method, computer program, semiconductor device
JP2001-318590 2001-10-16
PCT/JP2001/009616 WO2002037317A1 (en) 2000-11-02 2001-11-02 Parallel operation device, entertainment device, operating method, computer program, and semiconductor device

Publications (1)

Publication Number Publication Date
AU2002212702A1 true AU2002212702A1 (en) 2002-05-15

Family

ID=26603342

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002212702A Abandoned AU2002212702A1 (en) 2000-11-02 2001-11-02 Parallel operation device, entertainment device, operating method, computer program, and semiconductor device

Country Status (8)

Country Link
US (1) US20020143838A1 (en)
EP (1) EP1335299A4 (en)
JP (1) JP3338043B2 (en)
KR (1) KR100882113B1 (en)
CN (1) CN1320479C (en)
AU (1) AU2002212702A1 (en)
TW (1) TW571202B (en)
WO (1) WO2002037317A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050099641A (en) 2002-09-24 2005-10-14 인터디지탈 테크날러지 코포레이션 Computationally efficient mathematical engine
JP4046716B2 (en) * 2004-10-06 2008-02-13 株式会社ソニー・コンピュータエンタテインメント Information processing apparatus and data transmission method
JP3768516B1 (en) 2004-12-03 2006-04-19 株式会社ソニー・コンピュータエンタテインメント Multiprocessor system and program execution method in the system
JP2007122209A (en) * 2005-10-26 2007-05-17 Nec System Technologies Ltd Three-dimensional graphics drawing device, method therefor and program
JP4981398B2 (en) * 2006-10-05 2012-07-18 日本電信電話株式会社 Parallel computing system
KR100919236B1 (en) * 2007-05-22 2009-09-30 한국전자통신연구원 A method for 3D Graphic Geometric Transformation using Parallel Processor
CN102722412A (en) 2011-03-31 2012-10-10 国际商业机器公司 Combined computational device and method
US8893083B2 (en) 2011-08-09 2014-11-18 International Business Machines Coporation Collective operation protocol selection in a parallel computer
CN102411558B (en) * 2011-10-31 2015-05-13 中国人民解放军国防科学技术大学 Vector processor oriented large matrix multiplied vectorization realizing method
US9411726B2 (en) * 2014-09-30 2016-08-09 Samsung Electronics Co., Ltd. Low power computation architecture
US20230056246A1 (en) * 2021-08-03 2023-02-23 Micron Technology, Inc. Parallel matrix operations in a reconfigurable compute fabric

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3763365A (en) * 1972-01-21 1973-10-02 Evans & Sutherland Computer Co Computer graphics matrix multiplier
US6556044B2 (en) * 2001-09-18 2003-04-29 Altera Corporation Programmable logic device including multipliers and configurations thereof to reduce resource utilization
JPS58207177A (en) * 1982-05-28 1983-12-02 Nec Corp Arithmetic device
US5278781A (en) * 1987-11-12 1994-01-11 Matsushita Electric Industrial Co., Ltd. Digital signal processing system
US5222230A (en) * 1988-01-29 1993-06-22 Texas Instruments Incorporated Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges
US5311459A (en) * 1992-09-17 1994-05-10 Eastman Kodak Company Selectively configurable integrated circuit device for performing multiple digital signal processing functions
JPH07141325A (en) * 1993-11-17 1995-06-02 Oki Electric Ind Co Ltd Signal processor
JP3649478B2 (en) * 1995-07-20 2005-05-18 株式会社ソニー・コンピュータエンタテインメント Image information processing apparatus and image information processing method
US6247036B1 (en) * 1996-01-22 2001-06-12 Infinite Technology Corp. Processor with reconfigurable arithmetic data path
JP3203180B2 (en) * 1996-03-27 2001-08-27 三菱電機株式会社 Geometric operation device
DE19625569A1 (en) * 1996-06-26 1998-01-02 Philips Patentverwaltung Signal processor
US5889689A (en) * 1997-09-08 1999-03-30 Lucent Technologies Inc. Hierarchical carry-select, three-input saturation
CN1109990C (en) * 1998-01-21 2003-05-28 松下电器产业株式会社 Method and apparatus for arithmetic operation
JP3287305B2 (en) * 1998-04-23 2002-06-04 日本電気株式会社 Product-sum operation unit
US6477203B1 (en) * 1998-10-30 2002-11-05 Agilent Technologies, Inc. Signal processing distributed arithmetic architecture
US6526430B1 (en) * 1999-10-04 2003-02-25 Texas Instruments Incorporated Reconfigurable SIMD coprocessor architecture for sum of absolute differences and symmetric filtering (scalable MAC engine for image processing)
US6606700B1 (en) * 2000-02-26 2003-08-12 Qualcomm, Incorporated DSP with dual-mac processor and dual-mac coprocessor
US6557022B1 (en) * 2000-02-26 2003-04-29 Qualcomm, Incorporated Digital signal processor with coupled multiply-accumulate units

Also Published As

Publication number Publication date
JP2002202964A (en) 2002-07-19
EP1335299A4 (en) 2009-09-23
WO2002037317A1 (en) 2002-05-10
TW571202B (en) 2004-01-11
US20020143838A1 (en) 2002-10-03
CN1320479C (en) 2007-06-06
JP3338043B2 (en) 2002-10-28
KR20020069217A (en) 2002-08-29
KR100882113B1 (en) 2009-02-06
EP1335299A1 (en) 2003-08-13
CN1394314A (en) 2003-01-29

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