AU2001285384A1 - Enhancing performance by pre-fetching and caching data directly in a communication processor's register set - Google Patents

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set

Info

Publication number
AU2001285384A1
AU2001285384A1 AU2001285384A AU8538401A AU2001285384A1 AU 2001285384 A1 AU2001285384 A1 AU 2001285384A1 AU 2001285384 A AU2001285384 A AU 2001285384A AU 8538401 A AU8538401 A AU 8538401A AU 2001285384 A1 AU2001285384 A1 AU 2001285384A1
Authority
AU
Australia
Prior art keywords
fetching
communication processor
data directly
register set
caching data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001285384A
Inventor
Bruce G. Burns
Duane E. Galbi
Daniel J. Lussier
Wilson P. Snyder Ii
Joseph B. Tompkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Conexant Systems LLC
Original Assignee
Conexant Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/640,258 external-priority patent/US6754223B1/en
Application filed by Conexant Systems LLC filed Critical Conexant Systems LLC
Publication of AU2001285384A1 publication Critical patent/AU2001285384A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
AU2001285384A 2000-07-31 2001-07-31 Enhancing performance by pre-fetching and caching data directly in a communication processor's register set Abandoned AU2001285384A1 (en)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US22182100P 2000-07-31 2000-07-31
US60221821 2000-07-31
US09/640,258 US6754223B1 (en) 1999-08-17 2000-08-16 Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor
US09640258 2000-08-16
US09/639,915 US6888830B1 (en) 1999-08-17 2000-08-16 Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters
US09639915 2000-08-16
US09640231 2000-08-16
US09/640,231 US6804239B1 (en) 1999-08-17 2000-08-16 Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information
PCT/US2001/041485 WO2002011368A2 (en) 2000-07-31 2001-07-31 Pre-fetching and caching data in a communication processor's register set

Publications (1)

Publication Number Publication Date
AU2001285384A1 true AU2001285384A1 (en) 2002-02-13

Family

ID=27499249

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001285384A Abandoned AU2001285384A1 (en) 2000-07-31 2001-07-31 Enhancing performance by pre-fetching and caching data directly in a communication processor's register set

Country Status (2)

Country Link
AU (1) AU2001285384A1 (en)
WO (1) WO2002011368A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023843B2 (en) * 2002-06-26 2006-04-04 Nokia Corporation Programmable scheduling for IP routers
GB2466651A (en) * 2008-12-31 2010-07-07 St Microelectronics Security co-processor architecture for decrypting packet streams
GB0823702D0 (en) 2008-12-31 2009-02-04 St Microelectronics Res & Dev Processing packet streams
CN109300217B (en) * 2018-09-03 2021-03-12 深圳怡化电脑股份有限公司 Queuing and calling method, computer storage medium, queuing and calling server and system
CN114185513B (en) * 2022-02-17 2022-05-20 沐曦集成电路(上海)有限公司 Data caching device and chip

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5805927A (en) * 1994-01-28 1998-09-08 Apple Computer, Inc. Direct memory access channel architecture and method for reception of network information
US5920561A (en) * 1996-03-07 1999-07-06 Lsi Logic Corporation ATM communication system interconnect/termination unit

Also Published As

Publication number Publication date
WO2002011368A2 (en) 2002-02-07
WO2002011368A3 (en) 2002-06-06

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