AU2001275090A1 - Accessing state information in a hardware/software co-simulation - Google Patents

Accessing state information in a hardware/software co-simulation

Info

Publication number
AU2001275090A1
AU2001275090A1 AU2001275090A AU7509001A AU2001275090A1 AU 2001275090 A1 AU2001275090 A1 AU 2001275090A1 AU 2001275090 A AU2001275090 A AU 2001275090A AU 7509001 A AU7509001 A AU 7509001A AU 2001275090 A1 AU2001275090 A1 AU 2001275090A1
Authority
AU
Australia
Prior art keywords
simulation
hardware
software
state information
accessing state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001275090A
Inventor
Brian Bailey
Michael C. Brouhard
Jeffry A. Jones
Devon Kehoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mentor Graphics Corp
Original Assignee
Mentor Graphics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mentor Graphics Corp filed Critical Mentor Graphics Corp
Publication of AU2001275090A1 publication Critical patent/AU2001275090A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
AU2001275090A 2000-06-02 2001-05-31 Accessing state information in a hardware/software co-simulation Abandoned AU2001275090A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/587,496 2000-06-02
US09/587,496 US7072820B1 (en) 2000-06-02 2000-06-02 Accessing state information in a hardware/software co-simulation
PCT/US2001/017693 WO2001095160A2 (en) 2000-06-02 2001-05-31 Accessing state information in a hardware/software co-simulation

Publications (1)

Publication Number Publication Date
AU2001275090A1 true AU2001275090A1 (en) 2001-12-17

Family

ID=24350034

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001275090A Abandoned AU2001275090A1 (en) 2000-06-02 2001-05-31 Accessing state information in a hardware/software co-simulation

Country Status (4)

Country Link
US (1) US7072820B1 (en)
EP (1) EP1297457A2 (en)
AU (1) AU2001275090A1 (en)
WO (1) WO2001095160A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9195784B2 (en) * 1998-08-31 2015-11-24 Cadence Design Systems, Inc. Common shared memory in a verification system
GB0129596D0 (en) * 2001-12-11 2002-01-30 Nokia Corp Risk detection
US7409602B2 (en) * 2003-11-12 2008-08-05 Lsi Corporation Methodology for debugging RTL simulations of processor based system on chip
US7702789B2 (en) * 2005-11-03 2010-04-20 International Business Machines Corporation Apparatus, system, and method for reassigning a client
US8170020B2 (en) * 2005-12-08 2012-05-01 Microsoft Corporation Leveraging active firewalls for network intrusion detection and retardation of attack
JP4833907B2 (en) 2007-04-23 2011-12-07 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2008282308A (en) * 2007-05-14 2008-11-20 Nec Electronics Corp Cooperation verification device, cooperation verification method, and cooperation verification program
US20090055155A1 (en) * 2007-08-20 2009-02-26 Russell Klein Simulating execution of software programs in electronic circuit designs
US9075788B1 (en) * 2012-06-15 2015-07-07 Amazon Technologies, Inc. Account state simulation service for cloud computing environments
US9442696B1 (en) * 2014-01-16 2016-09-13 The Math Works, Inc. Interactive partitioning and mapping of an application across multiple heterogeneous computational devices from a co-simulation design environment
US10528685B2 (en) 2014-06-06 2020-01-07 Synopsys, Inc. Efficient mechanism in hardware and software co-simulation system
US10176078B1 (en) * 2015-08-28 2019-01-08 Cadence Design Systems, Inc. Debugging process
US11113440B1 (en) 2017-03-17 2021-09-07 Synopsys, Inc. Memory migration in hybrid emulation
US10922208B2 (en) 2018-05-31 2021-02-16 The Mathworks, Inc. Observer for simulation test and verification
US10684936B2 (en) * 2018-05-31 2020-06-16 The Mathworks, Inc. Observer for simulation test and verification
CN111949591A (en) * 2020-08-12 2020-11-17 珠海格力电器股份有限公司 Demonstrator display method, demonstrator, processor and movable equipment
CN115460121B (en) * 2022-11-07 2023-01-17 联通(广东)产业互联网有限公司 Data center monitoring method and system based on big data and digital twins

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768567A (en) * 1996-05-14 1998-06-16 Mentor Graphics Corporation Optimizing hardware and software co-simulator
US5771370A (en) * 1996-05-14 1998-06-23 Mentor Graphics Corporation Method and apparatus for optimizing hardware and software co-simulation
US6389379B1 (en) * 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6321366B1 (en) * 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6421251B1 (en) * 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6651225B1 (en) * 1997-05-02 2003-11-18 Axis Systems, Inc. Dynamic evaluation logic system and method
US6356862B2 (en) * 1998-09-24 2002-03-12 Brian Bailey Hardware and software co-verification employing deferred synchronization
US6263302B1 (en) * 1999-10-29 2001-07-17 Vast Systems Technology Corporation Hardware and software co-simulation including simulating the cache of a target processor
US6230114B1 (en) * 1999-10-29 2001-05-08 Vast Systems Technology Corporation Hardware and software co-simulation including executing an analyzed user program

Also Published As

Publication number Publication date
US7072820B1 (en) 2006-07-04
WO2001095160A3 (en) 2003-01-23
EP1297457A2 (en) 2003-04-02
WO2001095160A2 (en) 2001-12-13

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