AU2000237002A1 - Processor with cache divided for processor core and pixel engine uses - Google Patents
Processor with cache divided for processor core and pixel engine usesInfo
- Publication number
- AU2000237002A1 AU2000237002A1 AU2000237002A AU3700200A AU2000237002A1 AU 2000237002 A1 AU2000237002 A1 AU 2000237002A1 AU 2000237002 A AU2000237002 A AU 2000237002A AU 3700200 A AU3700200 A AU 3700200A AU 2000237002 A1 AU2000237002 A1 AU 2000237002A1
- Authority
- AU
- Australia
- Prior art keywords
- processor
- engine uses
- pixel engine
- cache divided
- processor core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
- G06F15/7846—On-chip cache and off-chip main memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2000/004008 WO2001061500A1 (en) | 2000-02-16 | 2000-02-16 | Processor with cache divided for processor core and pixel engine uses |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2000237002A1 true AU2000237002A1 (en) | 2001-08-27 |
Family
ID=21741066
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2000237002A Abandoned AU2000237002A1 (en) | 2000-02-16 | 2000-02-16 | Processor with cache divided for processor core and pixel engine uses |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2000237002A1 (en) |
WO (1) | WO2001061500A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6665775B1 (en) * | 2000-09-22 | 2003-12-16 | Intel Corporation | Cache dynamically configured for simultaneous accesses by multiple computing engines |
US20040225840A1 (en) * | 2003-05-09 | 2004-11-11 | O'connor Dennis M. | Apparatus and method to provide multithreaded computer processing |
US7873776B2 (en) | 2004-06-30 | 2011-01-18 | Oracle America, Inc. | Multiple-core processor with support for multiple virtual processors |
US7685354B1 (en) | 2004-06-30 | 2010-03-23 | Sun Microsystems, Inc. | Multiple-core processor with flexible mapping of processor cores to cache banks |
FR2993378B1 (en) * | 2012-07-12 | 2015-06-19 | Univ Bretagne Sud | DATA PROCESSING SYSTEM WITH ACTIVE CACHE |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5553262B1 (en) * | 1988-01-21 | 1999-07-06 | Mitsubishi Electric Corp | Memory apparatus and method capable of setting attribute of information to be cached |
US5761720A (en) * | 1996-03-15 | 1998-06-02 | Rendition, Inc. | Pixel engine pipeline processor data caching mechanism |
US5860158A (en) * | 1996-11-15 | 1999-01-12 | Samsung Electronics Company, Ltd. | Cache control unit with a cache request transaction-oriented protocol |
-
2000
- 2000-02-16 AU AU2000237002A patent/AU2000237002A1/en not_active Abandoned
- 2000-02-16 WO PCT/US2000/004008 patent/WO2001061500A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2001061500A1 (en) | 2001-08-23 |
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