AU2001249083A1 - High-speed data processing using internal processor memory space - Google Patents

High-speed data processing using internal processor memory space

Info

Publication number
AU2001249083A1
AU2001249083A1 AU2001249083A AU4908301A AU2001249083A1 AU 2001249083 A1 AU2001249083 A1 AU 2001249083A1 AU 2001249083 A AU2001249083 A AU 2001249083A AU 4908301 A AU4908301 A AU 4908301A AU 2001249083 A1 AU2001249083 A1 AU 2001249083A1
Authority
AU
Australia
Prior art keywords
data processing
memory space
speed data
processor memory
internal processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001249083A
Inventor
Terrence Hussey
Donald W. Monroe
Arnold N. Sodder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tenor Networks Inc
Original Assignee
Tenor Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tenor Networks Inc filed Critical Tenor Networks Inc
Publication of AU2001249083A1 publication Critical patent/AU2001249083A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9042—Separate storage for different parts of the packet, e.g. header and payload
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow
    • H04L49/9089—Reactions to storage capacity overflow replacing packets in a storage arrangement, e.g. pushout
    • H04L49/9094—Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Executing Machine-Instructions (AREA)
AU2001249083A 2000-03-03 2001-03-02 High-speed data processing using internal processor memory space Abandoned AU2001249083A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US18678200P 2000-03-03 2000-03-03
US60186782 2000-03-03
PCT/US2001/006901 WO2001067237A2 (en) 2000-03-03 2001-03-02 High-speed data processing using internal processor memory space

Publications (1)

Publication Number Publication Date
AU2001249083A1 true AU2001249083A1 (en) 2001-09-17

Family

ID=22686263

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001249083A Abandoned AU2001249083A1 (en) 2000-03-03 2001-03-02 High-speed data processing using internal processor memory space

Country Status (8)

Country Link
US (1) US7328277B2 (en)
EP (1) EP1261915A2 (en)
JP (1) JP2003526269A (en)
KR (1) KR20030007447A (en)
CN (1) CN1437724A (en)
AU (1) AU2001249083A1 (en)
CA (1) CA2402018A1 (en)
WO (1) WO2001067237A2 (en)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6847645B1 (en) * 2001-02-22 2005-01-25 Cisco Technology, Inc. Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node
US6952738B1 (en) * 2001-08-17 2005-10-04 Juniper Networks, Inc. Systems and methods for removing intrapacket gaps from streams of different bandwidths
US7113518B2 (en) 2001-12-19 2006-09-26 Agere Systems Inc. Processor with reduced memory requirements for high-speed routing and switching of packets
US7339943B1 (en) 2002-05-10 2008-03-04 Altera Corporation Apparatus and method for queuing flow management between input, intermediate and output queues
US7606248B1 (en) 2002-05-10 2009-10-20 Altera Corporation Method and apparatus for using multiple network processors to achieve higher performance networking applications
US7320037B1 (en) * 2002-05-10 2008-01-15 Altera Corporation Method and apparatus for packet segmentation, enqueuing and queue servicing for multiple network processor architecture
US7336669B1 (en) 2002-05-20 2008-02-26 Altera Corporation Mechanism for distributing statistics across multiple elements
US7593334B1 (en) 2002-05-20 2009-09-22 Altera Corporation Method of policing network traffic
US7304999B2 (en) * 2002-08-24 2007-12-04 Cisco Technology Inc. Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing engines
US7404015B2 (en) * 2002-08-24 2008-07-22 Cisco Technology, Inc. Methods and apparatus for processing packets including accessing one or more resources shared among processing engines
US20050281281A1 (en) * 2003-01-24 2005-12-22 Rajesh Nair Port input buffer architecture
US20040196843A1 (en) * 2003-02-20 2004-10-07 Alcatel Protection of network infrastructure and secure communication of control information thereto
US7581249B2 (en) * 2003-11-14 2009-08-25 Enterasys Networks, Inc. Distributed intrusion response system
US7522621B2 (en) * 2005-01-06 2009-04-21 International Business Machines Corporation Apparatus and method for efficiently modifying network data frames
US7551617B2 (en) 2005-02-08 2009-06-23 Cisco Technology, Inc. Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor
US7561589B2 (en) * 2005-02-23 2009-07-14 Cisco Technology, Inc Virtual address storage which may be of particular use in generating fragmented packets
US7606250B2 (en) 2005-04-05 2009-10-20 Cisco Technology, Inc. Assigning resources to items such as processing contexts for processing packets
US7739426B1 (en) 2005-10-31 2010-06-15 Cisco Technology, Inc. Descriptor transfer logic
US8006069B2 (en) 2006-10-05 2011-08-23 Synopsys, Inc. Inter-processor communication method
JP5094482B2 (en) * 2008-03-07 2012-12-12 キヤノン株式会社 Processing apparatus and processing method thereof
EP2400771B1 (en) * 2009-02-19 2014-11-19 Panasonic Corporation Recording medium, reproduction device, and integrated circuit
US9779057B2 (en) 2009-09-11 2017-10-03 Micron Technology, Inc. Autonomous memory architecture
US20120198551A1 (en) * 2011-01-31 2012-08-02 General Electric Company Method, system and device for detecting an attempted intrusion into a network
US8762802B2 (en) * 2011-12-01 2014-06-24 Shenzhen China Star Optoelectronics Technology Co., Ltd. Code checking method for a memory of a printed circuit board
US9779138B2 (en) 2013-08-13 2017-10-03 Micron Technology, Inc. Methods and systems for autonomous memory searching
US10003675B2 (en) 2013-12-02 2018-06-19 Micron Technology, Inc. Packet processor receiving packets containing instructions, data, and starting location and generating packets containing instructions and data
KR20160054850A (en) * 2014-11-07 2016-05-17 삼성전자주식회사 Apparatus and method for operating processors
WO2017074377A1 (en) * 2015-10-29 2017-05-04 Intel Corporation Boosting local memory performance in processor graphics
CN109479031B (en) * 2016-05-18 2021-06-25 马维尔以色列(M.I.S.L.)有限公司 Method and apparatus for processing packets in a network device
US10762030B2 (en) * 2016-05-25 2020-09-01 Samsung Electronics Co., Ltd. Storage system, method, and apparatus for fast IO on PCIE devices
CA3081591A1 (en) * 2017-11-06 2019-05-09 Pensando Systems Inc. Network system including match processing unit for table-based actions
US10877766B2 (en) 2018-05-24 2020-12-29 Xilinx, Inc. Embedded scheduling of hardware resources for hardware acceleration
US10705993B2 (en) * 2018-11-19 2020-07-07 Xilinx, Inc. Programming and controlling compute units in an integrated circuit
US11188497B2 (en) * 2018-11-21 2021-11-30 SambaNova Systems, Inc. Configuration unload of a reconfigurable data processor
US10848424B2 (en) * 2019-03-26 2020-11-24 Wipro Limited Method and system for improving switching capacity of software-based switches in access networks
CN111782273B (en) * 2020-07-16 2022-07-26 中国人民解放军国防科技大学 Software and hardware cooperative cache device for improving repeated program execution performance
US11386034B2 (en) 2020-10-30 2022-07-12 Xilinx, Inc. High throughput circuit architecture for hardware acceleration
US20240015108A1 (en) * 2020-11-20 2024-01-11 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for efficient input/output transfer in network devices

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5840214B2 (en) * 1979-06-26 1983-09-03 株式会社東芝 computer system
JPS63142449A (en) * 1986-12-04 1988-06-14 Fujitsu Ltd Patrol check system for control memory
US6038584A (en) 1989-11-17 2000-03-14 Texas Instruments Incorporated Synchronized MIMD multi-processing system and method of operation
US6070003A (en) 1989-11-17 2000-05-30 Texas Instruments Incorporated System and method of memory access in apparatus having plural processors and plural memories
JP3358254B2 (en) 1993-10-28 2002-12-16 株式会社日立製作所 Communication control device and communication control circuit device
EP0719065A1 (en) * 1994-12-20 1996-06-26 International Business Machines Corporation Multipurpose packet switching node for a data communication network
US5812549A (en) 1996-06-25 1998-09-22 International Business Machines Corporation Route restrictions for deadlock free routing with increased bandwidth in a multi-stage cross point packet switch
US6032190A (en) * 1997-10-03 2000-02-29 Ascend Communications, Inc. System and method for processing data packets
US6101599A (en) 1998-06-29 2000-08-08 Cisco Technology, Inc. System for context switching between processing elements in a pipeline of processing elements
US6279140B1 (en) * 1999-01-07 2001-08-21 International Business Machines Corporation Method and apparatus for checksum verification with receive packet processing
US6446196B1 (en) * 1999-02-17 2002-09-03 International Business Machines Corporation Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications
US6650640B1 (en) * 1999-03-01 2003-11-18 Sun Microsystems, Inc. Method and apparatus for managing a network flow in a high performance network interface

Also Published As

Publication number Publication date
WO2001067237A2 (en) 2001-09-13
KR20030007447A (en) 2003-01-23
US7328277B2 (en) 2008-02-05
CA2402018A1 (en) 2001-09-13
CN1437724A (en) 2003-08-20
WO2001067237A3 (en) 2002-04-25
EP1261915A2 (en) 2002-12-04
JP2003526269A (en) 2003-09-02
US20010049744A1 (en) 2001-12-06

Similar Documents

Publication Publication Date Title
AU2001249083A1 (en) High-speed data processing using internal processor memory space
AU2001237561A1 (en) Data access
AU2001261944A1 (en) Processor array and parallel data processing methods
GB2363018B (en) Processing image data
GB2363017B (en) Processing image data
GB2363020B (en) Processing image data
AU2001273282A1 (en) Post data processing
GB2363019B (en) Processing image data
GB0022970D0 (en) Data access
AU5616501A (en) Processing seismic data
GB0008561D0 (en) Processing image data
WO2002015055A8 (en) Data processing system
EP1281279B8 (en) Generic data processing engine
GB2359154B (en) Data processing
GB0007974D0 (en) Processing image data
GB0025050D0 (en) Object oriented data processing
IL151395A (en) Single instruction multiple data processing
AU2001269218A1 (en) Access control to data processing means
AU6964401A (en) Data processing system
GB2370893B (en) Single instruction multiple data processing
AU7433101A (en) Processing image data
GB0022953D0 (en) Processing buffered data
AU4863901A (en) Data processing
AU3969900A (en) Data processing in an access node
AU2001293509A1 (en) Data processing structure