JP2003526269A - High-speed data processing using internal processor memory area - Google Patents

Abstract

  (57) [Summary] The performance of a data processing system can be greatly improved by limiting the operation of the processor in its internal register file to reduce the number of instructions executed by the processor. Using direct memory access independent of the processor, data that is small enough to fit in the internal register file may be sent into the internal register file and execution results may be deleted from the internal register file. Thus, the processor can avoid executing load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activities are accessed and manipulated by the processor, which is completely in the internal register file.

Description

Detailed Description of the Invention

(Related Application) This application is a US provisional patent application No. 60/18 filed on Mar. 3, 2000.
Claim priority and benefits under 6,782. The entire application is incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION The present invention relates generally to information processing, and specifically to processing activities performed within internal components of a processor.

BACKGROUND OF THE INVENTION Data processing typically involves retrieving data from memory, processing the retrieved data, and storing the results of this processing activity back in memory. The hardware architecture that supports this data processing activity is typically
It controls the flow of information and the flow of control between the individual hardware units of the information processing system. One such hardware unit is a processor or processing engine, which includes arithmetic logic processing circuits, general purpose and special purpose registers, processing control or sequencing logic, and data paths connecting these components. . In some embodiments, the processor is provided as a custom designed integrated circuit, or is an application specific integrated circuit (A).
It is configured as an independent type central processing unit (CPU) provided in the SIC). The processor has internal registers for use with the operations defined by the set of instructions. Instructions are typically stored in instruction memory and specify a set of hardware functions available on the processor.

When providing these functions, the processor is typically "transient".
t) "data from memory external to the processor and executing a" load "instruction to load some of this data into internal registers sequentially or randomly and process the data in response to the instruction. , And using the “store” command,
Store the processed data back in the external memory. In addition to loading temporary data into internal registers and removing instruction results from internal registers, load and store instructions are also used cyclically during the actual processing of temporary data,
Access additional information needed to complete the processing activity (eg, access status register and command register). Cyclic load / store access to external memory is typically inefficient because the processor's execution capability is substantially faster than the processor's external interface capability. As a result, the processor is often idle while waiting for the accessed data to be loaded into the internal register file.

This inefficiency can be particularly limiting in devices operating within communication systems. This is because the net efficiency limits the overall data handling capacity of the device and limits the maximum data rate of the network itself unless some data is thinned out from the amount of data transmitted.

SUMMARY OF THE INVENTION The present invention provides a method for providing periodicity to external memory when a data set is small enough to be contained within the processor's local register file area allocated to process this data set. Understand that special access is not required. Therefore,
The present invention incorporates, at least in part, data access techniques that execute independently of the processor and avoid execution of load and store instructions by the processor.

In one embodiment, an information processing system and method incorporating one aspect of the invention limits the operation of an assigned processor to process a data set in the processor's internal register file. The information processing system includes a processor, an ingress element, and an egress element. The ingress element receives the raw data from the interface to a data source (eg, the data source corresponding to the network interface receiving the data from the communication network). The entry element sends the unprocessed data or a part thereof to the internal register file area of the processor by directly accessing the internal register file area. A unit for manipulating data in the processor (eg, an arithmetic logic unit) manipulates and processes the data in response to this data transfer to the processor's register file and generally operates within its internal register file area. Restrict. When this processing activity is complete, the exit element directly accesses the processed data and removes it from the internal register file area. Alternatively, the intermediate state machine directly accesses the processed data and forwards this data to the exit element.

In one aspect of the invention, one or more state machines are included within the inlet and outlet elements and govern the operation of the inlet and outlet elements. The state machine directly accesses the internal register file area of the processor to send data to or remove data from this area.
In one embodiment, the data transfer activity of the state machine is: a) signals by processor logic indicating the transfer of raw data at the entry element, b) transfer of raw data to the processor's register file area, c) command registers, etc. Is initiated in response to a change in the value stored in the logic element of the.

The benefits of the present invention may be realized in numerous information processing systems, such as focused processing systems such as image processing, signal processing, video processing, and network packet processing. As an example, the present invention may be implemented within a communication device such as a router and performs network services such as route processing, path determination, path switching functions and the like. The route processing function determines the type of routine required for the packet,
The path switching function, on the other hand, allows a router to receive a packet on one interface and forward it to a second interface. The path determination function selects the most appropriate interface for forwarding the packet.

To support the transmission of packets between multiple interfaces of a communication device, the path switching functionality of the communication device may be implemented within one or more forwarding engine ASICs incorporating aspects of the present invention. In this exemplary embodiment, the packet data is received via the communication network by ingress logic associated with a particular input port of the network interface of the communication device. A processor is then selected from the pool of candidate processors associated with the receiving port that processes the packet by the ingress logic.

After the processor is assigned, the packet is divided into a header part and a body part. The packet header is written by at least one state machine of the ingress logic configured to write to the packet header using direct memory / register access without the processor invoking a load or store instruction,
Written in a fixed location in a memory element, such as an internal register file associated with the assigned processor. The packet body is written to the output buffer. The processor then processes the packet header according to the locally stored instructions (again, the processor does not call a load or store instruction) and transmits the processed packet header to the selected output buffer.
In the output buffer, the packet header is embedded in the packet body, then
It is transmitted to the destination output port as it is transmitted from the communication device.

Prior to receiving the packet header, the assigned processor repeatedly executes the instruction stored at the first known location / address in the processor's instruction memory (eg, address 0) in an endless loop. The hardware inside the processor is
Detects that address 0 is the "special" address to which the hardwired instruction is returned, rather than the instruction from the instruction memory attached to the processor. When the packet header is transmitted from the ingress logic to the processor, the control signal indicates to the processor that header transmission is in progress. While this signal is active, the processor hardware forces the processor's program counter to a non-special address (eg, address 2), ending the execution of the infinite loop. Upon completing the transmission of the packet header, the processor begins executing instructions starting at address 2 of its instruction memory. When the packet processing activity is complete, the processor is reset (eg, the program counter is set to address 0) and the instruction is repeatedly executed at the above special address.

Thus, until the processor is ready to process the packet header, the processor writes the packet header directly to the processor's register file, without the need for any two-way communication or prior knowledge. Other information about the state or characteristics (eg, length) of the packet may also be stored locally in a register file using a similar procedure, which allows the processor to access an external source to obtain this information. There is no need.

To simplify the programming model of multiple processors, one processor may be assigned to each packet, with each processor configured to execute a common sequence of instructions in each instruction memory. Sufficient processors are allocated to ensure that packets can be processed at the wire / line rate of the communication network (ie, the maximum bit rate of the network interface). The reduced instruction set realized when incorporating aspects of the present invention into multiple processors within an ASIC reduces the die size of the ASIC. Therefore, the ASIC can be manufactured without suffering technical obstacles and adverse effects that occur during manufacturing.
It is possible to increase the density of the number of processors in the IC. The ASIC implementation of the present invention can be implemented, for example, by increasing the processor clock speed, by adding more processors to the ASIC, and by consolidating a pool of processors (having a common instruction set) from multiple ASICs. Further expansion is possible.

In one embodiment, the invention is used in a fully symmetric multiprocessing (SMP) system that presents a reduced instruction set computer (RISC) architecture for processing packets received over a communications network. obtain.
The SMP system includes a plurality of identical processors with common software acting as a pool, all of which are suitable for processing a particular packet. Each incoming packet is assigned to an available processor in the pool,
The processor processes packets simultaneously using a common instruction set. The SMP system reconstructs the processed packet stream to present the proper packet order.

The above description will be more readily understood from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION A typical microprocessor executes load and store instructions to represent temporary data structures stored in memory elements external to the processor for future execution. An image of static data into a local register of the processor. As used herein, the term "local register file" refers to the entire register in the internal structure of the processor that is available for use in manipulating data. "Registers" refer to different groups of storage elements such as D flip-flops. Depending on the processor design, the register file space may consist of memory and flip-flops. In either case, the register file is typically implemented using high speed memory components that provide multiple independently accessible read and write ports. During execution of a software program, a typical processor executes a relatively large number of load / store instructions to move data from external memory to a local register file and move execution results from the local register file to external memory. These frequent accesses to external memory are necessary because the data set to be processed is too large to fit in the execution area of the local register file.

In the present invention, frequent external memory accesses are necessary to process a data set small enough to be entirely located in the local register area (such as 128 to 512 8-bit data elements). Is not recognized. As described in detail below, the present invention combines direct memory access (DMA) and direct register access (DRA) techniques to move data and execution results into and out of a processor's register file. At this time, the processor does not need to execute instructions such as load and store instructions to move data. In this sense, DMA refers to a method of using one or more state machines to transfer a block of data to and from an internal memory or an external memory independently of a processor. Similarly, DRA refers to a particular type of DMA, that is, DMA that involves moving one or more blocks of data into and out of a processor's register file area independently of the processor. In one embodiment, a region of the register file has two write ports (as opposed to a 3-port register file having one write port and two read ports) to facilitate direct register file access. And as a 5-port register file area with 3 read ports. This approach avoids relatively slow external memory access (compared to what happens in the register file), avoids memory wait states,
It also reduces the size of the processor instruction set. As a result, and in addition to significantly increasing the performance of individual processors, the die size and power consumption of application specific integrated circuits (ASICs) including such processors are reduced, and the total number of processors in the ASIC is reduced. Can be significantly increased without incurring unbearable costs.

Although the present invention is described herein as being implemented in a network interface card of a communication device for processing packets received over a network, this particular implementation is merely It is an exemplary embodiment, and those skilled in the art will recognize any number of other embodiments and applications that may have the advantages of the present invention. For example, and without limitation, the present invention may be utilized in information processing applications involving relatively small data sets such as image processing, signal processing, and video processing. The present invention may also be implemented in a wide range of network communication devices (such as switches and routers) and other information processing embodiments.

Please refer to FIG. Communication device 150 may communicate information (eg, in the form of packages / frames, cells, or TDM frames) from communication network 110 via communication link 112, and may receive the received information from a different communication network or branch (local area network (LAN) 120). , Metropolitan Area Network (MAN
) 130, or a wide area network (WAN) 140, etc.) or a locally attached end station (not shown). Communication device 150 may include many network interface cards (NICs) such as NIC 160 and NIC 180. Each NIC has a series of ports (162, 16
4 and 166) and output ports (168, 170, and 172, etc.). The input ports 162, 164, and 166 are connected to the communication network 1
It receives information from 10 and forwards it to many packet processing engines (not shown). The packet processing engine is LAN1 including end stations
Process and prepare the packet for transmission on one of output ports 168, 170, and 172 corresponding to a communications network such as 20, MAN 130, or WAN 140.

Please refer to FIG. A network interface card (NIC) 160 embodying aspects of the invention includes input ports 162, 164 and 166, a packet processing or forwarding engine 220, an address lookup engine (ALE) 210, a statistics module 230, queuing / queuing. dequeuing
) Module 240 and output ports 168, 170 and 172. N
IC 160 receives packets from communication network 110 (FIG. 1) based on the packets at input ports 162, 164 and 166. Transfer engine 22
0, along with ALE 210, is the appropriate output port 168,17 associated with the destination.
The destination output port of the packet is determined by looking up 0 and 172 and prepending the transfer vector to the packet to help route it to the appropriate output port.

The modified packet is delivered to the dequeue / ingress module 240, which uses the transfer vector to organize the packet into a queue for a particular destination output port 168, 170, and 172. Then, the transfer vector of each packet is removed and the packet is transferred to the selected output ports 168, 170 and 1
Scheduled for transmission to 72. The packet is then transmitted from the selected output port 168, 170 and 172 to a communication network such as LAN 120, MAN 130 or WAN 140. In one embodiment,
The queuing module 240 of the NIC 160 has a full mesh interconnect (
The modified packet is received via (not shown), so that the packet originally received at the input port of either of the NICs 160 and 180 installed in the communication device 150 (the input port 162, 164 of its own NIC 160). And packets received by 166) to one or more of the output ports 168, 170 and 172 of its own NIC 160. In another embodiment, the packets received at input ports 162, 164 and 166 are forwarded by forwarding engine 220 directly to queuing module 240.

With reference to FIGS. 3 and 4, an example of the structure of the transfer engine 220 is an ingress logic 310, an ALE interface 350, and a statistics interface 36.
0, egress logic 370, and one or more processors shown as 320, 330, and 340, respectively. The operation is as follows. The data corresponding to the packet is transmitted via the communication network 110 and the NIC 160 or 180
Is received at a particular input port 162, 164 or 164 connected to the communication network 110 (step 410). After that, input ports 162, 164
Or 166 associated pooled processors (320, 33 respectively)
A processor 330 is selected from 0 and 340) to process the packet (step 420). Once the processor 330 is assigned, the packet
The entrance logic 310 divides the header and body (step 430).
). The packet header uses the processor 3 direct access to register
At a particular location in the register file 710 (FIG. 7) associated with 30, the packet body is written to the output buffer in egress logic 370 using direct access to memory (step 440). Processor 330 then processes the packet header according to the locally stored instructions (step 450).
, Transmit the processed packet header to egress logic 370, which recombines with the packet body at egress logic 370 (step 460).
).

Processor 330 may perform tasks such as processing packet headers as follows. Used to report the processing activity including the packet header by checking the integrity of the packet header, verifying the checksum, and accessing the statistics module 230 via the statistics interface 360. Provided statistics and communicate with ALE 210 via ALE interface 350. This allows output ports 168, 1
Obtain routing information for one of 70 and 172 associated with the destination of the packet. Additional network-specific (eg IP, ATM, Frame Relay, HDLC, TDM) packet processing may be done at this time. At the end of this processing activity, processor 330 modifies the packet header to cause NIC 16
Include routing information that specifies a particular output port 168, 170, 172 of 0 (eg, by prepending the transfer vector to the packet header). The modified packet header is then forwarded by egress logic 3 of forwarding engine 220.
70 and subsequently routed to egress logic 370 to queue / dequeue module 240 as described above.

The ALE interface 350, the statistics interface 360, and the exit logic 370 are included in the transfer engine 220 and include processors 320, 330 and 34.
It is a resource that can be shared between 0s. These resources 350, 360 and 37
An arbitration mechanism (not shown) in transfer engine 220 is provided in transfer engine 220 to arbitrate between processors 320, 330 and 340 for access to 0.
It is provided in 20. In one embodiment, when the processor 330 is assigned to a packet, the processor identifier, such as the processor number, for the processor 330 is
Each of the three shared resources 350, 360 and 370 described above are communicated. Each of these shared resources 350, 360 and 370 then writes the processor number to the FIFO, which is preferably the transfer engine 2
It has a depth equal to the total number of processors in 20. Shared resource 350,
The logic within each of 360 and 370 accesses the corresponding FIFO to
Determine which of the processors 320, 330 and 340 should then be allowed to access the resource. Allowed processor is a specific resource 3
Once the access to 50, 360, 370 is complete, the accessed resource reads the next FIFO entry to determine the next processor to which the grant should be issued.

Referring to FIGS. 5 and 6 in greater detail, the receipt, manipulation, and transmission of packet data within transfer engine 220 is primarily handled by multiple DMA and DRA state machines. In one embodiment, these state machines are housed within ingress logic 310 and processor 330. In operation of this embodiment, a packet is received from one of the input ports 162, 164 and 166 of the NIC 160 and received by the Receive_Data F in the ingress logic 310.
Stored in IFO (first-in / first-out buffer) 510 (
Step 610). The Receive_Status FIFO 512 records the particular input port 162, 164 or 164 at which the packet arrived and maintains an ordered list of the input port number of each packet received by the forwarding engine 220. The list is sorted according to when the packet was received.

The Issue_DMA_Command state machine 514 receives the Receive_DMA_Command state machine 514.
When the Status FIFO 512 accommodates the data and the Receive_sta
Detects whether to get the input port number associated with the input port 162, 164 or 166 that received the packet from the tus FIFO 512 (step 620).
). The Issue_DMA_Command state machine 514 then issues a processor allocation request containing the port number of the packet to the Allocate_Proce.
Send to sors state machine 516. Allocate_Processor
The state machine 516 uses the Allocation_Poo associated with the above port number.
l Register 518 is accessed to determine the set of processors 320, 330 and 340 that are candidates to operate on this packet (step 63).
0). The Allocate_Processor state machine 516 then
Access Processor_Free Register 520 and
Determines whether any of the candidate processors 320, 330 and 340 identified by the location_Pool Register 518 are available. The Allocate_Processor state machine 516 then allocates one of the available processors 330 from the set of candidate processors 320, 330 and 340 to process the packet (step 640).
), Assign permission of processor 330 and processor number to Issue_D
Send to MA_Command state machine 514.

Upon receiving the processor number associated with the assigned processor 310, I
The sue_DMA_Command state machine 514 sends an execution signal / command including the processor number to the DMA_Execute state machine 522. The DMA_Execute state machine 522 uses Header_DM
Access A_Length Register 524 to access processor 330
1. Acquire the amount of received packets to be sent (ie, the length of the packet header) (step 650). The DMA_Execute state machine 522 then
Issue a DMA command. The DMA command is Receive_Data F
The header portion of the packet (corresponding to the packet header) is taken out from the IFO 510 and transmitted via the DRA bus 526. On the DRA bus 526, the header portion of the packet is retrieved by the Processor_DRA state machine 530 included in the processor 330 (step 660). DMA_Exec
The ute state machine 522 further includes a Receive_Data FIFO5.
Issue a DMA command to retrieve the packet body from 10, and exit logic 37
0 DMA buffer 528 as received by a 0 buffer (not shown).
(Step 660). The Processor_DMA state machine 530 then continues the packet header data received via the DRA bus 526 from a fixed address location (eg, address 0) within the register file area 710 (FIG. 7) within the processor 330. (Step 670). Processor 330 then processes the packet header (step 680) and sends the processed header to egress logic 370 via Transmit_DMA state machine 532, where the processed header is recombined with the packet body (step 690). ).

More specifically, referring to FIGS. 7 and 8, the processing of the packet header within processor 330 is preferably such that the instructions and activities of the processor are executed in the local register file 710 of the execution region. Are limited to manipulating data and execution results in. The structure of the processor 330 in an exemplary embodiment is as follows: Status_Interface state machine 7
04, ALE_Interface state machine 706, Processor
_DRA state machine 530, Transmit_DMA state machine 53
2, register file 710, arithmetic logic unit (ALU) 720, processor control module 730, and instruction memory 740. Computing device 725 includes processor control 730 and ALU 720.

During this exemplary operation, and while the processor 330 is waiting to receive a packet header, the computing device 725 continually at a special address (eg, address 0) in the instruction memory 740. The instruction is executed (ie, in an endless loop) (step 810). Hardware within processor 330 detects that address 0 is a special address. At the special address, the instruction is stored in the instruction memory 740.
It comes back from the "hardwired" instruction value etched into the silicon, not the instruction stored in. In one possible implementation, accessing an instruction at a special address 0 returns a "JMP 0" (or jumps to the address 0 instruction), causing the processor 330 to execute an infinite loop at that address. Becomes

The packet header is transferred from the ingress logic 310 to the processor register file 7
If so, the control signal from Processor_DRA state machine 530 indicates to processor control module 730 that a packet header transfer is in progress (step 820). While this signal is active, the processor control module 730 causes the processor program counter (not shown) to identify a non-special address (eg, address 2) in the instruction memory 740 and causes the computing device 725 to specify the special address 0. Break the running infinite loop and wait until the signal is inactive (step 830). Computing device 725 begins executing the instruction at address 2 in response to the signal becoming inactive (step 84).
0). Address 2 of instruction memory 740 may be configured to hold the first instruction used to process the packet header in register file 710 (
That is, the instruction at address 2 corresponds to the start of the previously downloaded "real" software image to execute in the packet header). Proc
When the essor_DRA state machine 530 completes writing the packet header starting at a fixed location in the register file 710 (which occurs when the control signal becomes inactive), the computing device 725 will normally scan the remaining instructions in the instruction memory 740. Continue (ie, beyond address 2). A particular instruction in instruction memory 740 specifies a location in register file 710. When the processing activity for a particular packet header is complete, the executing software "jumps" to address 0 and executes the instruction at address 0 in an infinite loop. This technique illustrates one particular implementation of how processor 330 may be triggered to process packet headers stored in register file 710 without using load and store instructions.

In another embodiment, the assigned processor 330 may idle (ie, access instruction memory, etc.) until it receives a signal from the external state machine indicating that the complete packet header is in the register file 710. , Do not execute the instruction). After that, the computing device 725 may use the instruction memory 74.
Run the code from 0 to process the packet header. The trigger event may include, for example, when the control signal becomes inactive. Alternatively, the assigned processor 330 is triggered when the DRA transfer is initiated, completed, or being processed. Many other trigger events will be apparent to those skilled in the art.

As described above, processor 330 may process one or more shared resources external to processor 330 (eg, FIG. 3, ALE interface 350, statistics interface 360, and egress logic 370) during processing of packet headers. To access. For example, processor 330 interacts with ALE 210 (FIG. 2) via ALE interface 350 (FIG. 3) to initiate a search for ALE 210 and retrieve search results therefrom. Also, these interactions with ALE 210 performed by processor 330 occur without processor 330 loading and storing instructions.

In one aspect, and while executing instructions in instruction memory 740, processor 330 configures a search key starting at a given address in register file 710. The computing device 725 executes an instruction related to writing a value to the ALE_Command register that specifies the amount of search key data to be transferred to the ALE 210. This value effectively serves as a control line for the ALE_Interface state machine 706 of the processor 330, and the ALE_Interface
The ce state machine 706 uses direct memory access independent of the computing device 725 to read a value or other data from the ALE_command register, determine the amount of data to be transferred, and transfer the specified data to the ALE interface 350.
Trigger to transfer to. The processor 330 may perform other functions, such as authenticating a network protocol (eg, IP) checksum of the packet header while waiting for the results of the search to be returned. If the search results from ALE 210 are available, the search results are forwarded to ALE_Interface state machine 706 via ALE interface 350. ALE
The _Interface state machine 706 writes the search result to a predetermined location in the register file 710 using one or more direct register accesses and informs the computing device 725 when the write is complete. Computing device 725 subsequently modifies the packet header in response to the search results.

The processor 330 may also issue a statistics update command by writing the address and length values to the Statistics_Update_Command register (not shown) of the processor 330. S of processor 330
The statistics_Interface state machine 704 is the computing device 7.
25, using direct memory access independent of Statistics_Upd
Triggered to read data from the ate_Command register, determine the source and amount of data to transfer, and transfer the specified data to the statistics interface 360.

Similarly, when the processor 330 completes the processing of the packet header, the computing device 725 sends the processed packet header to the Transmi of the processor 330.
Write to the t_DMA state machine 532. Processor 330 transfers the processed header to a buffer at egress logic 370 using direct memory access independent of processor 330 (step 850). After all processing is complete, software execution in processor 330 jumps back to address 0 of instruction memory 740 and begins executing the infinite loop instruction previously described while waiting for the arrival of the next packet header ( Step 860).

More specifically, after the processing activity is completed, the packet header is transferred to the register file 7
Since it is not always necessary to make it resident in the ten adjacent areas,
It may be necessary to specify the location of each processed packet header in register file 710. Therefore, the arithmetic unit 725 is
e Issue one or more writes to the DMA Command Register (not shown) to specify the starting address and length of each processed packet header. These writes are effectively stored in the FIFO as a list of reassembly commands. After the data regarding all the fragmented packet headers are obtained, the arithmetic unit 725 determines that the Transmit DMA Co
Write to the mmand Register (not shown) to specify the body length of the packet along with other data.

When a value is written in the Transmit DMA Command Register, the Transmit DMA state machine 53 in the processor 330 is written.
2 is triggered to start the assembly of the packet header according to the reassembly command stored in the FIFO described above. After that, Transmit DM
The A state machine 532 sends the assembled packet header with specific control information (including the length of the packet body) to the egress logic 370 using a direct memory access method independent of the arithmetic unit 725. The egress logic 370 concatenates the processed packet header received from the Transmit DMA state machine 532 with the packet body stored in the egress logic 370 FIFO, and then queues the reassembled packet as described above. / Transmit to the dequeuing module 240.

In order to properly reconstruct the packet header with the packet body, the processor 33
0 obtains the total length of the packet from the data embedded in the packet header itself, and the Receive Data FIFO 510 (FIG. 5) causes the processor 3
Obtain the packet header length from the data sent to 30 (this corresponds to the value written to the header length register 524 of FIG. 5). Based on this information, the processor 330 calculates the amount of packet body data previously sent to the output FIFO in the egress logic 370 and determines the length of the packet body in the Transmit
Designated as control information to be sent by DMA state machine 532 to egress logic 370. In this way, the processor 330 causes the exit logic 3
It is possible to specify the amount of data in the packet body to be extracted from the output FIFO of 70 and added to the newly assembled packet header formed by the processor 330, thereby reconstructing the modified packet. be able to. In order to properly reconstruct the modified packet, the processor 330
Access to egress logic 370 is granted in the same order in which processor 330 was assigned (and thus the same order that the packet bodies were written to the output FIFO of egress logic 370).

Aspects of the invention provide a great deal of flexibility in allocating computational resources to incoming packet processing requirements. Processors 320, 330 in transfer engine 220,
Assuming that the total number of 340 is 40 for exemplary purposes, the processor 32
0, 330, 340 can be flexibly assigned to meet the packet processing requirements of multiple input / output port configurations. For example, in the NIC 160 having only one logical input port (that is, port 0), 40 processors 320, 33
All 0, 340 can be assigned to handle packets for that one port. In this scenario, the code images loaded in the instruction memory 740 of each processor 320, 330, 340 can be the same,
Each processor 320, 330, 340 can perform the same algorithm for its one type of input port. In another scenario where there are four logical input ports, each of which comprises a different type of network interface, the processing algorithms required for different network interfaces may be different. In this case, 40 processors can be assigned as follows: processor [0-9] assigned to port 0, processor [10-19] assigned to port 1, processor [2029] assigned to port. 2 and then processors [30-39] to port 3. In addition, four different code images are downloaded, each unique image corresponding to a particular input port. In yet another scenario, the NIC 160
May include two logical input ports, each of which has different processing performance requirements. In such a scenario, one of these input ports may consume 75% of the ingress bus bandwidth and has a packet arrival rate that requires 75% of the processor's resources and the other port Occupy the rest. To support these performance requirements, 30 processors may be assigned to input port 0 and 10 processors may be assigned to input port 1.

NICs 160, 1 that incorporate multiple processors as part of their forwarding engine 220 by assigning one processor to each received packet.
The programming model for 80 can be simplified. Further, as noted above, the die size reduction achieved by the system incorporating the present invention allows additional processors to be provided within the transfer engine ASICs of the NICS 160, 180, resulting in packet transmission of the network 110. The wire rate can be surely performed. The present invention is based on a given transfer engine ASIC.
It can be easily scaled by adding a processor on top of it to increase the clock rate of the processor and by integrating the processing pools of multiple ASICs. In providing this capability, the hardware architecture of the present invention maintains the ordering of packets arriving through the network interface, which causes reassembled packets to be sent from the forwarding engine in the proper order. Note that this is possible.

To give an example where this processor pool integration technique is particularly advantageous, the line rate at which the NIC 160 of the communication device 150 receives the packet data stream via the communication network 110 (when not using this integration technique). NI
There is a situation where the processing capacity of C160 may be exceeded, resulting in dropped packets and poor quality of service. Using this integration technique, it is possible to allocate idle processors from one or more transfer engines. For example, NIC1
60 may include multiple forwarding engine ASICs, each of which comprises a pool of processors that may be assigned to handle packets arriving at any input port on NIC 160. Alternatively, the communication device 15
A pool of processors in additional forwarding engine ASICS residing on other NICs 180 in 0 may also be assigned to the NIC 160, which has a heavy network load.

While the present invention has been described with reference to particular details, such details are a limitation on the scope of the invention, except as to and to the extent of the claims below. It is intended that it should not be considered as a thing.

[Brief description of drawings]

FIG. 1 schematically shows a communication device for connecting a communication network to other networks such as LAN, MAN and WAN.

2 schematically illustrates some components of a network interface card installed in the communication device of FIG. 1, according to one embodiment of the invention.

3 schematically illustrates some components of a forwarding engine that form part of the network interface card of FIG. 2, according to one embodiment of the invention.

FIG. 4 provides a flow diagram of the steps performed when operating the forwarding engine of FIG. 3, according to one embodiment of the invention.

5 schematically illustrates some components of the ingress logic of FIG. 3 and a processor of the forwarding engine that perform direct memory and direct register access, according to one embodiment of the invention.

FIG. 6 provides a flow diagram of the steps performed during operation of the ingress logic and processor of FIG. 5, according to one embodiment of the invention.

FIG. 7 schematically illustrates a more detailed set of components forming the processor of FIG. 5, according to one embodiment of the invention.

FIG. 8 provides a flow diagram of the steps performed when operating the processor component shown in FIG. 7, according to one embodiment of the invention.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CO, CR, CU, CZ, DE , DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, I S, JP, KE, KG, KP, KR, KZ, LC, LK , LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, P T, RO, RU, SD, SE, SG, SI, SK, SL , TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor Monroe, Donald W.             United States Massachusetts             01741, Carlisle, Patch Meadow               Lane 75 (72) Inventor Soda, Arnold N.             United States Massachusetts             02460, Newtonville, Oak             Rifroad 44 F-term (reference) 5K030 GA03 HA08 HD01 KA03 KA12                       KA15

Claims (29)

[Claims] 1. A method of processing a packet, the steps of receiving the packet, identifying a packet header portion of the data packet, and transmitting the packet header to a register file accessible to a processor. And processing the packet header without invoking at least one load and store instructions by the processor. 2. The method of claim 1, wherein the transmitting step is performed without invoking at least one load and store instruction. 3. The packet is divided into the packet header portion and the packet body portion, the packet header is transmitted to the register file using direct register access, and the packet body is transmitted to an output buffer. The method of claim 1, further comprising: 4. Selecting an output port for transmitting the packet, integrating the processed packet header with the packet body in the output buffer, and combining the integrated packet with the output buffer. To the selected output port for transmission from there. 4. The method of claim 3, further comprising: 5. Providing a plurality of identical processors to execute a general instruction set, each processor storing the instruction set locally in the processor, and the packet header The method of claim 1, further comprising: selecting a processor from the plurality of processors for processing, causing the selected processor to process the packet header. 6. The method of claim 5, wherein selecting the processor is performed by a state machine responsive to receiving the packet at an input port. 7. The step of causing the selected processor to process the packet header includes writing the packet header to at least one fixed location in the register file accessible to the selected processor. The method of claim 5, performed by at least one configured state machine. 8. The method of claim 5, further comprising downloading a general instruction set into instruction memory within each of the plurality of processors. 9. A method of processing a packet header of a packet received via a communication network, the method comprising: sending the packet header to at least one fixed location in the register file; Providing an associated processor, the processor repeatedly executing instructions in an infinite loop, the instructions being stored at a first known location in an instruction memory associated with the processor; Causing the processor to execute an instruction from a second known location in the instruction memory in response to transmitting the packet header, the instruction starting at the second known location in the instruction memory According to what is done in the at least one fixed location in the register file Processing a packet header, and resetting the processor to repeatedly execute the instruction stored at the first known location in the instruction memory after processing the packet header. , Including a method. 10. The method of claim 9, wherein the processing step comprises processing the packet header without invoking at least one load and store instruction. 11. A step of receiving the packet at an input port connected to the communication network, a step of selecting the processor from a plurality of candidate processors associated with the input port, the packet including the packet header and a packet. Process of dividing into main body and DRA issued by state machine connected to the register file
The method of claim 9, further comprising: executing the command to send the packet header to the at least one fixed location in the register file associated with the selected processor. 12. The method of claim 11, further comprising downloading a general instruction set into instruction memory in each of the plurality of candidate processors. 13. A packet processing system for processing a packet received via a communication network, the input port being configured to receive the packet via the communication network, the input port being associated with the input port. A processor, a register file accessible to the processor, an input element connected to the input port, the processor, and the register file, the entrance element comprising at least one of the packets by invoking a DRA command. An entry element configured to send a portion to the register file, the processor responsive to the DRA command without invoking at least one load instruction and a store instruction in the register file. Process the at least a portion of the packet That, packet processing system. 14. The packet processing system of claim 13, wherein the ingress element is configured to select the processor from a plurality of candidate processors associated with the input port. 15. A plurality of instruction memories are further included, each of the plurality of instruction memories being associated with a corresponding processor of the plurality of candidate processors, the plurality of instruction memories including the same instruction set. The packet processing system according to claim 14. 16. The packet processing system of claim 13, wherein the at least a portion of the packet corresponds to a header of the packet. 17. The packet processing system of claim 16, wherein the ingress element comprises a state machine configured to write the packet header to a fixed location within the register file. 18. A packet processing system for processing a packet header of a packet received via a communication network, comprising: an input port connected to the communication network; and a packet header connected to the input port to obtain the packet header. An ingress element configured to receive and parse the packet for storing the packet header received from the ingress element connected to the ingress element at at least one fixed location A register file, an instruction memory configured to return instructions from at least first and second addresses, the entry element, the register file, and a processor connected to the instruction memory, the processor comprising: Repeats the instructions stored in the first instruction memory. And running, the processor is responsive to signals from said inlet element, in order to process the packet header of the register file, the instruction said memory 2
A packet processing system including a processor that executes instructions from an address of. 19. An information processing system, a processor having an internal register file area for operating data and a unit, an entry element for sending unprocessed data to the internal register file area, and the internal register file area. An exit element for deleting processed data from the processor, the operation of the processor being restricted to manipulate the data in the internal register file area. 20. At least one state machine for controlling the operation of said ingress and egress elements and responsive to an instruction in said internal register file area, said state machine being in accordance with said instruction. 20. The system of claim 19, further comprising at least one state machine that moves data in and out of the internal register file area using direct access to. 21. The system of claim 20, further comprising a network interface that receives data from a communication network, the interface providing the received data to the ingress element. 22. A method of processing information, comprising providing a processor having an internal register file area for manipulating data and a unit, and sending unprocessed data to the internal register file area, and A step of deleting processed data from the internal register file area using direct access to the internal register file area, the operation of the processor to manipulate the data in the internal register file area. A method, comprising the steps of: 23. Providing at least one state machine for controlling the sending of data to and the deletion of data from the internal register file area using direct access to the internal register file area. Causing the processor to signal the state machine by writing the value in a control register, the state machine responsive to the value and performing the direct access by state machine logic, 23. The method of claim 22, further comprising: 24. The method of claim 22, wherein the unprocessed data is provided by a communication network having a line data rate and the processor processes the data at a rate equal to the line rate. 25. The unprocessed data is in the form of packets,
The method of claim 24. 26. A method of processing a packet stream containing a temporal sequence of packets, the method comprising providing a plurality of identical processors executing a general instruction set, each processor Storing the instruction set locally; receiving the packet; (i) identifying a packet header portion of the data packet for each packet; (ii) a processor from the plurality of processors. Selecting to process the packet header based on processor availability; and (iii) causing the selected processor to process the packet header using the locally stored instructions. Collecting the processed packets and replaying the packet stream according to the temporary sequence, Method. 27. The method of claim 26, wherein the plurality of processors are physically located on a plurality of integrated circuits. 28. A system for processing a packet stream containing a temporary sequence of packets, the plurality of identical processors executing a general instruction set, each processor comprising a local instruction containing the instruction set. A processor including a memory, an input port for receiving the packet, and an ingress logic unit connected to the input port and the processor, the ingress logic unit comprising: (i) for each packet Identifying a packet header portion, and (ii) selecting a processor from the plurality of processors,
The selected processor is configured to process the packet header based on processor availability, the selected processor processing the packet header using the locally stored instruction. And an egress logic unit that collects the processed packets and reproduces the packet stream according to the temporary sequence. 29. The system of claim 28, wherein the plurality of processors are physically located on a plurality of integrated circuits.