AU2001283458A1 - Method and apparatus for crossing clock domain boundaries - Google Patents

Method and apparatus for crossing clock domain boundaries

Info

Publication number
AU2001283458A1
AU2001283458A1 AU2001283458A AU8345801A AU2001283458A1 AU 2001283458 A1 AU2001283458 A1 AU 2001283458A1 AU 2001283458 A AU2001283458 A AU 2001283458A AU 8345801 A AU8345801 A AU 8345801A AU 2001283458 A1 AU2001283458 A1 AU 2001283458A1
Authority
AU
Australia
Prior art keywords
clock domain
predetermined number
data
domain boundaries
crossing clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283458A
Inventor
Brian Johnson
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU2001283458A1 publication Critical patent/AU2001283458A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)

Abstract

A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.
AU2001283458A 2000-08-21 2001-08-21 Method and apparatus for crossing clock domain boundaries Abandoned AU2001283458A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09642090 2000-08-21
US09/642,090 US6333893B1 (en) 2000-08-21 2000-08-21 Method and apparatus for crossing clock domain boundaries
PCT/US2001/025955 WO2002017325A1 (en) 2000-08-21 2001-08-21 Method and apparatus for crossing clock domain boundaries

Publications (1)

Publication Number Publication Date
AU2001283458A1 true AU2001283458A1 (en) 2002-03-04

Family

ID=24575155

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001283458A Abandoned AU2001283458A1 (en) 2000-08-21 2001-08-21 Method and apparatus for crossing clock domain boundaries

Country Status (9)

Country Link
US (2) US6333893B1 (en)
EP (2) EP2290657B1 (en)
JP (1) JP5138857B2 (en)
KR (1) KR100607773B1 (en)
CN (1) CN1291417C (en)
AT (2) ATE490539T1 (en)
AU (1) AU2001283458A1 (en)
DE (1) DE60143581D1 (en)
WO (1) WO2002017325A1 (en)

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US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US7058799B2 (en) * 2001-06-19 2006-06-06 Micron Technology, Inc. Apparatus and method for clock domain crossing with integrated decode
JP2003044349A (en) * 2001-07-30 2003-02-14 Elpida Memory Inc Register and signal generating method
JP4812976B2 (en) * 2001-07-30 2011-11-09 エルピーダメモリ株式会社 Register, memory module and memory system
US6661554B2 (en) * 2001-08-23 2003-12-09 Cyoptics (Israel) Ltd. Biasing of an electro-optical component
US6952791B2 (en) * 2001-12-03 2005-10-04 Broadcom Corporation Method and circuit for initializing a de-skewing buffer in a clock forwarded system
US6774687B2 (en) * 2002-03-11 2004-08-10 Micron Technology, Inc. Method and apparatus for characterizing a delay locked loop
US6966022B1 (en) * 2002-04-04 2005-11-15 Adaptec, Inc. System and method for determining integrated circuit logic speed
US6900685B2 (en) * 2002-05-16 2005-05-31 Micron Technology Tunable delay circuit
US6801070B2 (en) 2002-05-16 2004-10-05 Micron Technology, Inc. Measure-controlled circuit with frequency control
US7319728B2 (en) 2002-05-16 2008-01-15 Micron Technology, Inc. Delay locked loop with frequency control
US6983354B2 (en) 2002-05-24 2006-01-03 Micron Technology, Inc. Memory device sequencer and method supporting multiple memory device clock speeds
US7085905B2 (en) * 2002-07-18 2006-08-01 Sun Microsystems, Inc. Memory data stretcher
US20040013003A1 (en) * 2002-07-19 2004-01-22 Micron Technology, Inc. First bit data eye compensation for open drain output driver
US6865135B2 (en) 2003-03-12 2005-03-08 Micron Technology, Inc. Multi-frequency synchronizing clock signal generator
US7299329B2 (en) 2004-01-29 2007-11-20 Micron Technology, Inc. Dual edge command in DRAM
US7171321B2 (en) * 2004-08-20 2007-01-30 Rambus Inc. Individual data line strobe-offset control in memory systems
US7084680B2 (en) * 2004-08-31 2006-08-01 Micron Technology, Inc. Method and apparatus for timing domain crossing
US7301831B2 (en) * 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US9809278B2 (en) * 2004-09-28 2017-11-07 Shimano, Inc. Apparatus for reducing an engaging force of an engaging member
US7543172B2 (en) 2004-12-21 2009-06-02 Rambus Inc. Strobe masking in a signaling system having multiple clock domains
US7688672B2 (en) * 2005-03-14 2010-03-30 Rambus Inc. Self-timed interface for strobe-based systems
US7526704B2 (en) * 2005-08-23 2009-04-28 Micron Technology, Inc. Testing system and method allowing adjustment of signal transmit timing
US20080005709A1 (en) * 2006-06-30 2008-01-03 International Business Machines Corporation Verification of logic circuits using cycle based delay models
US7685542B2 (en) * 2007-02-09 2010-03-23 International Business Machines Corporation Method and apparatus for shutting off data capture across asynchronous clock domains during at-speed testing
US8108738B2 (en) * 2007-06-26 2012-01-31 International Business Machines Corporation Data eye monitor method and apparatus
US7779375B2 (en) * 2007-10-17 2010-08-17 International Business Machines Corporation Design structure for shutting off data capture across asynchronous clock domains during at-speed testing
US7500132B1 (en) * 2008-04-11 2009-03-03 International Business Machines Corporation Method of asynchronously transmitting data between clock domains
US8132036B2 (en) * 2008-04-25 2012-03-06 International Business Machines Corporation Reducing latency in data transfer between asynchronous clock domains
US20120110244A1 (en) * 2010-11-02 2012-05-03 Micron Technology, Inc. Copyback operations
US9008196B2 (en) * 2011-04-28 2015-04-14 International Business Machines Corporation Updating interface settings for an interface
US9225322B2 (en) 2013-12-17 2015-12-29 Micron Technology, Inc. Apparatuses and methods for providing clock signals
US8929152B1 (en) 2014-04-02 2015-01-06 Altera Corporation Retiming programmable devices incorporating random access memories
KR102251813B1 (en) * 2015-04-07 2021-05-13 삼성전자주식회사 Memory System and Operating Method of Memory System
US10313099B1 (en) * 2018-06-04 2019-06-04 MACOM Technology Solutions Holding, Inc. Multi-lane coherent transceiver with synchronized lane reset signals
US10999050B1 (en) 2020-05-04 2021-05-04 Stmicroelectronics International N.V. Methods and apparatus for data synchronization in systems having multiple clock and reset domains

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US4286255A (en) * 1979-02-22 1981-08-25 Burroughs Corporation Signature verification method and apparatus
JPS573283A (en) * 1980-06-03 1982-01-08 Hitachi Denshi Ltd Readout system for data
US4899339A (en) * 1987-10-09 1990-02-06 Kabushiki Kaisha Toshiba Digital multiplexer
US5487092A (en) 1994-12-22 1996-01-23 International Business Machines Corporation System for high-speed synchronization across clock domains
JP3612634B2 (en) * 1996-07-09 2005-01-19 富士通株式会社 Input buffer circuit, integrated circuit device, semiconductor memory device, and integrated circuit system corresponding to high-speed clock signal
US5951635A (en) * 1996-11-18 1999-09-14 Vlsi Technology, Inc. Asynchronous FIFO controller
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
JP3922765B2 (en) 1997-07-22 2007-05-30 富士通株式会社 Semiconductor device system and semiconductor device
US5915107A (en) 1997-09-26 1999-06-22 Advanced Micro Devices, Inc. Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other
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JP2000040363A (en) * 1998-05-21 2000-02-08 Nec Corp Semiconductor memory
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Also Published As

Publication number Publication date
CN1447975A (en) 2003-10-08
EP1312094B1 (en) 2010-12-01
EP2290657A1 (en) 2011-03-02
CN1291417C (en) 2006-12-20
KR100607773B1 (en) 2006-08-01
ATE557396T1 (en) 2012-05-15
EP2290657B1 (en) 2012-05-09
DE60143581D1 (en) 2011-01-13
KR20030028813A (en) 2003-04-10
JP2004507033A (en) 2004-03-04
US6414903B1 (en) 2002-07-02
JP5138857B2 (en) 2013-02-06
EP1312094A1 (en) 2003-05-21
US20020021616A1 (en) 2002-02-21
ATE490539T1 (en) 2010-12-15
WO2002017325A1 (en) 2002-02-28
US6333893B1 (en) 2001-12-25

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