AU2001266828A1 - Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs - Google Patents

Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs

Info

Publication number
AU2001266828A1
AU2001266828A1 AU2001266828A AU6682801A AU2001266828A1 AU 2001266828 A1 AU2001266828 A1 AU 2001266828A1 AU 2001266828 A AU2001266828 A AU 2001266828A AU 6682801 A AU6682801 A AU 6682801A AU 2001266828 A1 AU2001266828 A1 AU 2001266828A1
Authority
AU
Australia
Prior art keywords
layout
inputs
outputs
segmented ball
ball limited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001266828A
Inventor
Krishna Sheshan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001266828A1 publication Critical patent/AU2001266828A1/en
Abandoned legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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Abstract

The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying bond pad.
AU2001266828A 2000-06-28 2001-06-07 Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs Abandoned AU2001266828A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/606,319 2000-06-28
US09/606,319 US7034402B1 (en) 2000-06-28 2000-06-28 Device with segmented ball limiting metallurgy
PCT/US2001/018750 WO2002001637A2 (en) 2000-06-28 2001-06-07 Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs

Publications (1)

Publication Number Publication Date
AU2001266828A1 true AU2001266828A1 (en) 2002-01-08

Family

ID=24427488

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001266828A Abandoned AU2001266828A1 (en) 2000-06-28 2001-06-07 Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs

Country Status (9)

Country Link
US (3) US7034402B1 (en)
EP (1) EP1297571B1 (en)
CN (1) CN1255875C (en)
AT (1) ATE378691T1 (en)
AU (1) AU2001266828A1 (en)
DE (1) DE60131402T2 (en)
HK (1) HK1052081A1 (en)
MY (2) MY152171A (en)
WO (1) WO2002001637A2 (en)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) * 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US7902679B2 (en) * 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6541303B2 (en) * 2001-06-20 2003-04-01 Micron Technology, Inc. Method for conducting heat in a flip-chip assembly
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
JP3742057B2 (en) 2002-12-25 2006-02-01 株式会社バッファロー Analysis technology of radio wave condition in wireless information communication
JP4758614B2 (en) * 2003-04-07 2011-08-31 ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． Electroplating composition and method
KR100520239B1 (en) * 2003-06-17 2005-10-11 삼성전자주식회사 signal bus lines layout in semiconductor device and method therefore
JP2005012209A (en) * 2003-06-17 2005-01-13 Samsung Electronics Co Ltd Signal bus line layout structure in semiconductor device and its method
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
US7326859B2 (en) * 2003-12-16 2008-02-05 Intel Corporation Printed circuit boards having pads for solder balls and methods for the implementation thereof
US8067837B2 (en) 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
US7187078B2 (en) * 2004-09-13 2007-03-06 Taiwan Semiconductor Manufacturing Co. Ltd. Bump structure
DE102004046699A1 (en) * 2004-09-24 2006-04-13 Infineon Technologies Ag Contact surfaces e.g. cooling unit, connecting device, has contact surfaces connected by solidifying liquid e.g. melted solder, such that section of one of two surface edges exhibits structuring in area of edges
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US7375431B1 (en) * 2005-03-18 2008-05-20 National Semiconductor Corporation Solder bump formation in electronics packaging
US8405220B1 (en) 2005-03-23 2013-03-26 Marvell International Ltd. Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types
US7586199B1 (en) * 2005-03-23 2009-09-08 Marvell International Ltd. Structures, architectures, systems, methods, algorithms and software for configuring and integrated circuit for multiple packaging types
US7420280B1 (en) 2005-05-02 2008-09-02 National Semiconductor Corporation Reduced stress under bump metallization structure
US20070001301A1 (en) * 2005-06-08 2007-01-04 Yongqian Wang Under bump metallization design to reduce dielectric layer delamination
JP4890835B2 (en) * 2005-10-28 2012-03-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
EP2007273B1 (en) * 2006-04-07 2017-01-25 Novarix Ltd. Vein navigation device
US7635643B2 (en) * 2006-04-26 2009-12-22 International Business Machines Corporation Method for forming C4 connections on integrated circuit chips and the resulting devices
US20080284009A1 (en) * 2007-05-16 2008-11-20 Heikyung Min Dimple free gold bump for drive IC
WO2009013826A1 (en) * 2007-07-25 2009-01-29 Fujitsu Microelectronics Limited Semiconductor device
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
US7911803B2 (en) * 2007-10-16 2011-03-22 International Business Machines Corporation Current distribution structure and method
US20090189298A1 (en) * 2008-01-28 2009-07-30 Fu-Chung Wu Bonding pad structure and debug method thereof
US8212357B2 (en) * 2008-08-08 2012-07-03 International Business Machines Corporation Combination via and pad structure for improved solder bump electromigration characteristics
US8916464B2 (en) 2008-12-29 2014-12-23 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US7985671B2 (en) * 2008-12-29 2011-07-26 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US7871919B2 (en) * 2008-12-29 2011-01-18 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US9859235B2 (en) * 2009-01-26 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Underbump metallization structure
TWI394253B (en) * 2009-03-25 2013-04-21 Advanced Semiconductor Eng Chip having bump and package having the same
US8299611B2 (en) 2009-04-08 2012-10-30 International Business Machines Corporation Ball-limiting-metallurgy layers in solder ball structures
US8084858B2 (en) * 2009-04-15 2011-12-27 International Business Machines Corporation Metal wiring structures for uniform current density in C4 balls
KR101652386B1 (en) * 2009-10-01 2016-09-12 삼성전자주식회사 Integrated circuit chip and method of manufacturing the same and flip chip package having the integrated chip and method of manufacturing the same
GB2482894B (en) 2010-08-18 2014-11-12 Cambridge Silicon Radio Ltd Interconnection structure
JP5581972B2 (en) * 2010-10-27 2014-09-03 アイシン・エィ・ダブリュ株式会社 Electronic component and electronic device
US8963326B2 (en) 2011-12-06 2015-02-24 Stats Chippac, Ltd. Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration
TWI490992B (en) * 2011-12-09 2015-07-01 Chipmos Technologies Inc Semiconductor structure
US8624404B1 (en) * 2012-06-25 2014-01-07 Advanced Micro Devices, Inc. Integrated circuit package having offset vias
CN104080270A (en) * 2013-03-25 2014-10-01 飞思卡尔半导体公司 Separation pad for circuit board
KR20150059835A (en) * 2013-11-25 2015-06-03 에스케이하이닉스 주식회사 Semiconductor device having TSV
KR20160009425A (en) * 2014-07-16 2016-01-26 에스케이하이닉스 주식회사 Semiconductor device having a TSV and method of fabricating the same
US11257774B2 (en) * 2014-08-31 2022-02-22 Skyworks Solutions, Inc. Stack structures in electronic devices including passivation layers for distributing compressive force
US9871013B2 (en) 2014-12-29 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Contact area design for solder bonding
KR102440119B1 (en) 2017-08-10 2022-09-05 삼성전자주식회사 Semiconductor package and method of fabricating the same
US20200006273A1 (en) * 2018-06-28 2020-01-02 Intel Corporation Microelectronic device interconnect structure
CN111613596B (en) * 2019-02-25 2022-01-14 中芯国际集成电路制造(上海)有限公司 Package structure and method for forming the same

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6016103B2 (en) 1977-09-13 1985-04-23 セイコーエプソン株式会社 semiconductor integrated circuit
JPS5444881A (en) 1977-09-16 1979-04-09 Nec Corp Electrode wiring structure of integrated circuit
US4233337A (en) * 1978-05-01 1980-11-11 International Business Machines Corporation Method for forming semiconductor contacts
JPS57106056A (en) 1980-12-23 1982-07-01 Mitsubishi Electric Corp Electrode structural body of semiconductor device
JPS607758A (en) 1983-06-27 1985-01-16 Nec Corp Semiconductor device
JPS6149452A (en) 1984-08-17 1986-03-11 Matsushita Electronics Corp Semiconductor element
JPS62176140A (en) 1986-01-30 1987-08-01 Seiko Epson Corp Shape of pad in semiconductor integrated circuit
DE3815266A1 (en) * 1988-05-05 1989-11-16 Metallgesellschaft Ag ELECTROLYSIS
JPH0319248A (en) 1989-06-15 1991-01-28 Nec Corp Semiconductor device
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
FR2658509B1 (en) 1990-02-22 1992-06-12 Roussel Uclaf
US5089877A (en) * 1990-06-06 1992-02-18 Sgs-Thomson Microelectronics, Inc. Zero power ic module
JPH0513418A (en) 1991-07-04 1993-01-22 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JP2988075B2 (en) * 1991-10-19 1999-12-06 日本電気株式会社 Semiconductor device
JPH05166814A (en) * 1991-12-13 1993-07-02 Fujitsu Ltd Solder bump and manufacture thereof
JPH05206198A (en) 1992-01-29 1993-08-13 Nec Corp Semiconductor device
US5578526A (en) * 1992-03-06 1996-11-26 Micron Technology, Inc. Method for forming a multi chip module (MCM)
JP3383329B2 (en) * 1992-08-27 2003-03-04 株式会社東芝 Method for manufacturing semiconductor device
US5436412A (en) * 1992-10-30 1995-07-25 International Business Machines Corporation Interconnect structure having improved metallization
US5410184A (en) 1993-10-04 1995-04-25 Motorola Microelectronic package comprising tin-copper solder bump interconnections, and method for forming same
US5426266A (en) * 1993-11-08 1995-06-20 Planar Systems, Inc. Die bonding connector and method
JPH07335679A (en) 1994-06-03 1995-12-22 Fujitsu Ten Ltd Soldering structure for aluminum post
US5492863A (en) * 1994-10-19 1996-02-20 Motorola, Inc. Method for forming conductive bumps on a semiconductor device
US5492235A (en) 1995-12-18 1996-02-20 Intel Corporation Process for single mask C4 solder bump fabrication
US6300688B1 (en) * 1994-12-07 2001-10-09 Quicklogic Corporation Bond pad having vias usable with antifuse process technology
JPH08204136A (en) * 1995-01-31 1996-08-09 Rohm Co Ltd Semiconductor device
KR100327442B1 (en) * 1995-07-14 2002-06-29 구본준, 론 위라하디락사 Bump structure of semiconductor device and fabricating method thereof
US5674780A (en) 1995-07-24 1997-10-07 Motorola, Inc. Method of forming an electrically conductive polymer bump over an aluminum electrode
JPH0982714A (en) 1995-09-14 1997-03-28 Citizen Watch Co Ltd I/o terminal of semiconductor integrated circuit
JP3457123B2 (en) * 1995-12-07 2003-10-14 株式会社リコー Semiconductor device
KR100216839B1 (en) * 1996-04-01 1999-09-01 김규현 Solder ball land structure of bga semiconductor package
US5903058A (en) * 1996-07-17 1999-05-11 Micron Technology, Inc. Conductive bumps on die for flip chip application
US5883435A (en) * 1996-07-25 1999-03-16 International Business Machines Corporation Personalization structure for semiconductor devices
JP3629872B2 (en) 1997-01-24 2005-03-16 日本ゼオン株式会社 Aromatic vinyl-conjugated diene block copolymer and process for producing the same
JPH10270484A (en) 1997-03-25 1998-10-09 Matsushita Electron Corp Semiconductor device and manufacture thereof
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
JP3592486B2 (en) * 1997-06-18 2004-11-24 株式会社東芝 Soldering equipment
US6121065A (en) * 1997-09-26 2000-09-19 Institute Of Microelectronics Wafer scale burn-in testing
US6875681B1 (en) 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
US6927491B1 (en) * 1998-12-04 2005-08-09 Nec Corporation Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board
SG93278A1 (en) * 1998-12-21 2002-12-17 Mou Shiung Lin Top layers of metal for high performance ics
US6075712A (en) * 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip
US6179200B1 (en) * 1999-02-03 2001-01-30 Industrial Technology Research Institute Method for forming solder bumps of improved height and devices formed
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6387734B1 (en) * 1999-06-11 2002-05-14 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
KR20010004529A (en) * 1999-06-29 2001-01-15 김영환 wafer level package and method of fabricating the same
US6596624B1 (en) * 1999-07-31 2003-07-22 International Business Machines Corporation Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier
JP4021104B2 (en) * 1999-08-05 2007-12-12 セイコーインスツル株式会社 Semiconductor device having bump electrodes
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
JP2001196413A (en) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp Semiconductor device, method of manufacturing the same, cmp device and method
TW437030B (en) * 2000-02-03 2001-05-28 Taiwan Semiconductor Mfg Bonding pad structure and method for making the same
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6495917B1 (en) * 2000-03-17 2002-12-17 International Business Machines Corporation Method and structure of column interconnect
JP2001291720A (en) * 2000-04-05 2001-10-19 Hitachi Ltd Semiconductor integrated circuit device and its manufacturing method
JP4750926B2 (en) * 2000-06-06 2011-08-17 富士通セミコンダクター株式会社 Semiconductor device
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
JP3523189B2 (en) * 2000-12-27 2004-04-26 株式会社東芝 Semiconductor device
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
DE10109799A1 (en) * 2001-03-01 2002-09-05 Henkel Kgaa 3in1 dishwashing detergent and process for producing the same
JP4248761B2 (en) * 2001-04-27 2009-04-02 新光電気工業株式会社 Semiconductor package, manufacturing method thereof, and semiconductor device
US6686664B2 (en) * 2001-04-30 2004-02-03 International Business Machines Corporation Structure to accommodate increase in volume expansion during solder reflow
US6437431B1 (en) * 2001-08-07 2002-08-20 Lsi Logic Corporation Die power distribution system
JP3548553B2 (en) * 2001-10-10 2004-07-28 Ｎｅｃマイクロシステム株式会社 Semiconductor device and power supply wiring method between internal power supply terminals thereof
US20030122258A1 (en) * 2001-12-28 2003-07-03 Sudhakar Bobba Current crowding reduction technique using slots
US6841413B2 (en) * 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
FR2842351A1 (en) * 2002-07-12 2004-01-16 St Microelectronics Sa ADAPTATION OF AN INTEGRATED CIRCUIT TO SPECIFIC NEEDS
US7023067B2 (en) * 2003-01-13 2006-04-04 Lsi Logic Corporation Bond pad design
US6913946B2 (en) * 2003-06-13 2005-07-05 Aptos Corporation Method of making an ultimate low dielectric device
US7329951B2 (en) * 2005-04-27 2008-02-12 International Business Machines Corporation Solder bumps in flip-chip technologies
TWI295498B (en) * 2005-09-30 2008-04-01 Siliconware Precision Industries Co Ltd Semiconductor element with conductive bumps and fabrication method thereof

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WO2002001637A2 (en) 2002-01-03
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US20050158980A1 (en) 2005-07-21
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