JPS62176140A - Shape of pad in semiconductor integrated circuit - Google Patents

Shape of pad in semiconductor integrated circuit

Info

Publication number
JPS62176140A
JPS62176140A JP61018669A JP1866986A JPS62176140A JP S62176140 A JPS62176140 A JP S62176140A JP 61018669 A JP61018669 A JP 61018669A JP 1866986 A JP1866986 A JP 1866986A JP S62176140 A JPS62176140 A JP S62176140A
Authority
JP
Japan
Prior art keywords
pad
divided
parts
pads
slit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61018669A
Other languages
Japanese (ja)
Inventor
Yoshiteru Ono
芳照 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP61018669A priority Critical patent/JPS62176140A/en
Publication of JPS62176140A publication Critical patent/JPS62176140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the effects to other parts such as an output driver and the like, to prevent erroneous operation and to enhance the stabilization of a system, without separating and increasing pads, by providing a slit in a power supplying pad, and dividing one power source pad into two or more parts. CONSTITUTION:With a contact part made to remain, an aluminum layer 1 at a pad part is divided with a slit 2. The contact part 3 is made to remain so that operation can be recognized even if a needle is contacted to either of the divided pads when evaluation is performed with a probe card. Connection is performed with a bonding ball 4. The effects of potential fluctuation and the like to a pad part 6 from a pad part 5 are reduced because the signal passes through a bonding resistance. The stability of a system can be enhanced without separating and increasing the pads. When the power supplying pad is divided into three parts with the slits, the same effect can be obtained as in the case of the pad is divided into two parts.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 大発明は半導体集積回路の電源供給用パッドにおけるパ
ッド形状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of a power supply pad of a semiconductor integrated circuit.

〔発明の概要〕[Summary of the invention]

大発明は半導体集積回路において電源供給用パッドにス
リット？持たせ、１つの電源パッドな２つ以上に分割し
、ワイヤポンディング状態で１本のワイヤより２つ以上
の電源供給箇所へ電源供給することにより、消費電流ｈ
ｔ多く、電圧変動の大きい部分の影響な、ボンディング
抵抗１通してワイヤーへ導き、他方の部分へはボンディ
ング抵抗により変動が伝搬しずらくすることＫより、集
積回路内の電圧な安定させ、誤動作？防ぐものでちる。The great invention is a slit in the power supply pad in semiconductor integrated circuits? By dividing one power pad into two or more parts and supplying power to two or more power supply points from one wire in a wire bonding state, the current consumption h can be reduced.
In order to stabilize the voltage within the integrated circuit and cause malfunctions, the bonding resistor makes it difficult for the fluctuations to propagate to the other part. ? It's something to prevent.

〔従来の技術〕[Conventional technology]

従来、図５に示すように、電源供給は、半導体集積回路
内の電源を安定にする之めに、入艷ンーバー、内部セル
、出力ドライバー等、個別に電源パッド？用意して安定
させるか、あるいは１つな・図６に示すようにパッドを
中心にして２方向以上に分配し、消費電流が多く、電源
変動の多い部分の影響を、他の少ない方向へ伝搬させな
いようにし、誤動作な防止する方法が用いられていた。Conventionally, as shown in Fig. 5, power supply has been carried out using individual power pads for the input module, internal cells, output drivers, etc. in order to stabilize the power supply within the semiconductor integrated circuit. Either prepare it and stabilize it, or distribute it in two or more directions around the pad as shown in Figure 6, and propagate the influence of the part with high current consumption and large power fluctuations to other directions with less power. Methods were used to prevent malfunctions.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし１図５に示すような従来技術では、入力レシーバ
ー、内部セル、出力ドライ、＜−等の電源供給用パッド
を、分離、増設してゆく必要がちる。However, in the conventional technique as shown in FIG. 5, it is necessary to separate and add power supply pads for input receivers, internal cells, output drivers, <-, etc.

これは現在及び、これから先の将来に渡って要求され続
けてゆく半導体集積回路の多ピン化現象の中で、使用可
能なパッド数を電源供給用パッド尤よって減少させてし
まうという問題点？有していた。まｔ１図６に示すよう
な従来技術では、パッドのアルミ層ｈ″−低インピーダ
ンスでちり、出力ドライバー等の影響ｈ’−パッド部分
を介して伝搬してしまい、大評な効果ｈ′−見られない
とい５問題点？有していた。Is this a problem in that the number of usable pads, especially the power supply pads, will be reduced in the current and future demand for semiconductor integrated circuits with more pins? had. In the conventional technology as shown in Fig. 6, the influence of dust, output driver, etc. due to the low impedance of the aluminum layer h'' of the pad propagates through the pad portion, resulting in the highly acclaimed effect h''. There were 5 problems that could not be solved.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、半導体集積回路において、入力
レシーバー、内部セル、出力ドライバー等による電源併
給用パッドの分離、増設シすることをく、それらの影響
を低減させ、回路の誤動作？防止し、システムの安定性
な高めるためのバンド形状？得ることにある。The present invention is intended to solve these problems, and its purpose is to avoid the need to separate or add power supply pads for input receivers, internal cells, output drivers, etc. in semiconductor integrated circuits. , reduce their effects and circuit malfunction? Band shape to prevent and increase system stability? It's about getting.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路におけるパッド形状は電源供給
用パッドにおいて、スリットによりパッド？２つ以上に
分割することを特徴とする。The shape of the pad in the semiconductor integrated circuit of the present invention is that the power supply pad is formed by a slit. It is characterized by being divided into two or more parts.

〔実施例〕〔Example〕

以下に本発明の実施例を図面にもとづいて説明する。笛
１図は本発明により電源供給用バンドシスリットによっ
て２つに分割し念場合の実施例を示す。１けパッド部分
のアルミ層であり、３の接触部？残して、これをスリッ
ト２によって２分割したものである。２け１つのパッド
？２つに分割する几めのスリットでちり、３けプローブ
カードによる評価の際Ｋ、２分割したパッドのうち、ど
ちら側に針が当っても動作確認ができるようにするため
に残し几接触部である。Embodiments of the present invention will be described below based on the drawings. Fig. 1 shows an embodiment in which the whistle is divided into two parts by a power supply band system slit according to the present invention. Is it the aluminum layer of the 1st pad part and the contact part of 3rd? This is divided into two by slit 2. 2 but 1 pad? The fine slit that divides the pad into two prevents dust, and during evaluation using the 3-piece probe card, the contact area is left behind so that operation can be confirmed no matter which side of the pad that is divided into two is touched by the needle. It is.

図３及び図４は、本発明により電源供給バンドな、スリ
ットにより３分割し之場合の実施例？示す。この場合も
スリット、接触部の役割は、バシドシ２分割した場合と
同様である。3 and 4 show an embodiment in which the power supply band is divided into three by slits according to the present invention. show. In this case as well, the roles of the slit and contact portion are the same as in the case of dividing the shell into two parts.

図２Ｆ′ｉ、図１の断面図である。このよ５に４のポン
ディングポールで接続することにより、５のパッド部分
から６のパッド部分への電位変動等の影響がポンディン
グ抵抗を介するために減少されバヴドシ分離、増設する
ことをく、システムの安定性な高めることｈｔ可能にな
る。FIG. 2F'i is a cross-sectional view of FIG. 1; By connecting 5 to the pad 4 in this way, the influence of potential fluctuations from the pad 5 to the pad 6 is reduced through the bonding resistor, making it unnecessary to separate or add more pads. It becomes possible to increase the stability of the system.

〔発明の効果〕〔Effect of the invention〕

以上述べｔように、この発明によれば、パッドにスリッ
トを持たせるという簡単な形状によってパッドを分離、
増設することをく、出力ドライバー等の他への影響を低
減し、誤動作を防止しシステムの安定化？高める効果が
ある。As described above, according to the present invention, the pad can be separated by a simple shape of having a slit in the pad.
Does it eliminate the need for expansion, reduce the impact on other devices such as output drivers, prevent malfunctions, and stabilize the system? It has the effect of increasing

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明にかかる２分割したパッド図。 第２図は、２分割したパッド縦断面図。 第３図、＠４図は、３分割し之パ１ド図。 第５図、第６図は、従来の電源供給用パッド図でちる。 １、５．６．７．９．１１．１２．１５　・・・・・・
パッドアルミ配線 ２．８．１０　　　・・・・・・　ス　　リ　　ッ　　
ト３・・・・・・接触部FIG. 1 is a diagram of a pad divided into two parts according to the present invention. FIG. 2 is a longitudinal sectional view of the pad divided into two parts. Figures 3 and 4 are 1-dot diagrams divided into three parts. 5 and 6 are diagrams of conventional power supply pads. 1, 5.6.7.9.11.12.15 ・・・・・・
Pad aluminum wiring 2.8.10 ・・・・・・ Slip
G3...Contact part

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路の電源供給用パッドにおいて、１つのパ
ッドをスリットにより２つ以上に分割することを特徴と
する半導体集積回路におけるパッド形状。A pad shape for a semiconductor integrated circuit, characterized in that one pad is divided into two or more by a slit in a power supply pad for a semiconductor integrated circuit.
JP61018669A 1986-01-30 1986-01-30 Shape of pad in semiconductor integrated circuit Pending JPS62176140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61018669A JPS62176140A (en) 1986-01-30 1986-01-30 Shape of pad in semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61018669A JPS62176140A (en) 1986-01-30 1986-01-30 Shape of pad in semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS62176140A true JPS62176140A (en) 1987-08-01

Family

ID=11978010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61018669A Pending JPS62176140A (en) 1986-01-30 1986-01-30 Shape of pad in semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS62176140A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
WO2002001637A3 (en) * 2000-06-28 2002-09-26 Intel Corp Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053850A (en) * 1988-03-14 1991-10-01 Motorola, Inc. Bonding pad for semiconductor devices
WO2002001637A3 (en) * 2000-06-28 2002-09-26 Intel Corp Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs
US7034402B1 (en) 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing

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