AU2001245686A1 - Method and apparatus for reducing back-to-back voltage glitch on high speed databus - Google Patents

Method and apparatus for reducing back-to-back voltage glitch on high speed databus

Info

Publication number
AU2001245686A1
AU2001245686A1 AU2001245686A AU4568601A AU2001245686A1 AU 2001245686 A1 AU2001245686 A1 AU 2001245686A1 AU 2001245686 A AU2001245686 A AU 2001245686A AU 4568601 A AU4568601 A AU 4568601A AU 2001245686 A1 AU2001245686 A1 AU 2001245686A1
Authority
AU
Australia
Prior art keywords
voltage level
voltage
high speed
logically
driver transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001245686A
Inventor
Jen-Tai Hsu
Hing Y. To
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001245686A1 publication Critical patent/AU2001245686A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
  • Details Of Television Scanning (AREA)

Abstract

An example embodiment of a method and apparatus for reducing back-to-back voltage glitch on a high speed bus is described. A pre-driver circuit receives an input voltage signal whose voltage level swings from a logically low voltage level to a logically high voltage level where the logically low voltage level approximately equals VSS and the logically high voltage level approximately equals VCC. The pre-driver circuit reduces the magnitude of the voltage swing to create a signal that when delivered to a driver transistor ensures that the driver transistor will operate in its saturation region even when the voltage on the high speed bus is at its minimum specified voltage. When the driver transistor operates in its saturation region it can sink a constant current and provide a high output impedance.
AU2001245686A 2000-03-31 2001-03-13 Method and apparatus for reducing back-to-back voltage glitch on high speed databus Abandoned AU2001245686A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/540,822 US6507218B1 (en) 2000-03-31 2000-03-31 Method and apparatus for reducing back-to-back voltage glitch on high speed data bus
US09540822 2000-03-31
PCT/US2001/008067 WO2001075615A2 (en) 2000-03-31 2001-03-13 Method and apparatus for reducing back-to-back voltage glitch on high speed data bus

Publications (1)

Publication Number Publication Date
AU2001245686A1 true AU2001245686A1 (en) 2001-10-15

Family

ID=24157074

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001245686A Abandoned AU2001245686A1 (en) 2000-03-31 2001-03-13 Method and apparatus for reducing back-to-back voltage glitch on high speed databus

Country Status (10)

Country Link
US (1) US6507218B1 (en)
EP (1) EP1269326B1 (en)
KR (1) KR100510758B1 (en)
CN (1) CN1432157A (en)
AT (1) ATE331251T1 (en)
AU (1) AU2001245686A1 (en)
DE (1) DE60120944T2 (en)
HK (1) HK1049533B (en)
TW (1) TW514792B (en)
WO (1) WO2001075615A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7471107B1 (en) 2004-05-12 2008-12-30 Pmc-Sierra, Inc. Active biasing in metal oxide semiconductor (MOS) differential pairs
US7898295B1 (en) 2009-03-19 2011-03-01 Pmc-Sierra, Inc. Hot-pluggable differential signaling driver
US8547140B1 (en) 2010-11-03 2013-10-01 Pmc-Sierra, Inc. Apparatus and method for generating a bias voltage
WO2019087602A1 (en) * 2017-11-02 2019-05-09 ソニーセミコンダクタソリューションズ株式会社 Electronic circuit and electronic apparatus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179299A (en) * 1990-11-05 1993-01-12 Ncr Corporation Cmos low output voltage bus driver
US5128560A (en) 1991-03-22 1992-07-07 Micron Technology, Inc. Boosted supply output driver circuit for driving an all N-channel output stage
JP2848500B2 (en) * 1991-04-04 1999-01-20 三菱電機株式会社 Interface system
US5781034A (en) * 1996-07-11 1998-07-14 Cypress Semiconductor Corporation Reduced output swing with p-channel pullup diode connected
US5969554A (en) 1997-06-09 1999-10-19 International Business Machines Corp. Multi-function pre-driver circuit with slew rate control, tri-state operation, and level-shifting
KR100237898B1 (en) * 1997-07-10 2000-01-15 김영환 Semiconductor circuit generating high voltage power
US6040737A (en) 1998-01-09 2000-03-21 S3 Incorporated Output buffer circuit and method that compensate for operating conditions and manufacturing processes
US6184700B1 (en) * 1999-05-25 2001-02-06 Lucent Technologies, Inc. Fail safe buffer capable of operating with a mixed voltage core

Also Published As

Publication number Publication date
EP1269326A2 (en) 2003-01-02
CN1432157A (en) 2003-07-23
KR100510758B1 (en) 2005-08-26
ATE331251T1 (en) 2006-07-15
WO2001075615A3 (en) 2002-01-31
HK1049533A1 (en) 2003-05-16
TW514792B (en) 2002-12-21
DE60120944D1 (en) 2006-08-03
DE60120944T2 (en) 2007-01-04
WO2001075615A2 (en) 2001-10-11
HK1049533B (en) 2006-12-08
US6507218B1 (en) 2003-01-14
KR20020091169A (en) 2002-12-05
EP1269326B1 (en) 2006-06-21

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