KR970068167A - Tri-state output circuit - Google Patents

Tri-state output circuit Download PDF

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Publication number
KR970068167A
KR970068167A KR1019960009549A KR19960009549A KR970068167A KR 970068167 A KR970068167 A KR 970068167A KR 1019960009549 A KR1019960009549 A KR 1019960009549A KR 19960009549 A KR19960009549 A KR 19960009549A KR 970068167 A KR970068167 A KR 970068167A
Authority
KR
South Korea
Prior art keywords
output
control signal
unit
latch unit
signal
Prior art date
Application number
KR1019960009549A
Other languages
Korean (ko)
Other versions
KR0157955B1 (en
Inventor
김대휘
강희복
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019960009549A priority Critical patent/KR0157955B1/en
Publication of KR970068167A publication Critical patent/KR970068167A/en
Application granted granted Critical
Publication of KR0157955B1 publication Critical patent/KR0157955B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

Abstract

본 발명은 삼상태 출력회로에 관한 것으로 출력신호(OUT)는 충분한 삼상태의 값을 갖지 못함으로 인해서 출력 스윙(swing)레벨이 커지고 이로인해 입력에 따른 출력의 응답속도가 지연될 수 있는 문제점이 발생할 수 있으며, 이러한 문제점을 해결하기 위하여 본 발명은, 프리-리셋 기법을 이용하여 출력단의 천이시간을 줄여 안정된 삼상태를 만들어서 입력에 따른 출력의 빠른 응답을 얻을 수 있게되어 빠른 엑세스 타임을 요구하는 디바이스에 적용할 수 있는 효과가 있으며 삼상태로 되는 기간이 짧은 경우에도 유용하게 사용할 수 있는 효과가 있다. 또한 기존의 출력 버퍼용 트랜지스터를 그대로 이용하게 되어 레이아웃 면에서 효과적이다.The present invention relates to a tristate output circuit, in which the output swing level is increased due to the fact that the output signal (OUT) does not have a sufficient tristate value and thus the response speed of the output according to the input can be delayed In order to solve such a problem, the present invention can reduce the transition time of the output stage by using the pre-reset technique, thereby making the stable tri-state and obtain a quick response of the output according to the input, There is an effect that can be applied to a device, and it can be advantageously used even in a case where the period of three states is short. In addition, since the conventional transistor for output buffer is used as it is, it is effective in layout.

Description

삼상태 출력회로Tri-state output circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명 삼상태 출력회로의 상세회로도.FIG. 2 is a detailed circuit diagram of the tristate output circuit of the present invention. FIG.

Claims (1)

입력신호를 반전시키는 피모스, 엔모스 트랜지스터와 인에이블신호에 따라 전원전압고 접지전압을 상기 모스 트랜지스터에 공급 또는 차단하는 인버터 및 피모스, 엔모스 트랜지스터로 이루어진 래치부와; 상기 래치부의 출력 신호와 제어신호를 논리조합하는 제어신호입력부와; 상기 래치부와 같은 구조로 이루어져 상기 인에이블신호에 따라 상기 래치부의 출력을 반전함으로써 원래의 입력신호를 출력하는 역할을 하는 이전데이타 래치부와; 제어신호가 하이상태에서 로우상태로 변하는 시점을 포착하여 짧은 기간동안 펄스를 출력하는 제어신호 감지부와; 상기 제어신호감지부의 출력펄스와 상기 이전데이타 래치부의 출력을 조합하여 상기 제어신호입력부의 출력과 논리조합하는 프리-리셋궤환부와; 이 프리-리셋궤환부의 출력신호에 따라 전원전압을 외부로 출력 또는 차단하는 출력부로 구성하여 된 것을 특징으로 하는 삼상태 출력회로.An inverter for supplying or interrupting a power supply voltage and a ground voltage to the MOS transistor in accordance with a PMOS transistor and an NMOS transistor for inverting an input signal, and a latch unit comprising a PMOS transistor and an NMOS transistor; A control signal input unit for logically combining an output signal of the latch unit and a control signal; A previous data latch unit having the same structure as the latch unit and serving to output an original input signal by inverting the output of the latch unit according to the enable signal; A control signal sensing unit for sensing a time point at which the control signal changes from a high state to a low state and outputting a pulse for a short period of time; A pre-reset feedback unit which combines the output pulse of the control signal sensing unit and the output of the previous data latch unit and logically combines the output pulse of the control signal input unit and the output of the control signal input unit; And an output section for outputting or cutting off the power supply voltage to the outside according to an output signal of the pre-reset feedback section. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960009549A 1996-03-30 1996-03-30 Three state output circuit KR0157955B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009549A KR0157955B1 (en) 1996-03-30 1996-03-30 Three state output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009549A KR0157955B1 (en) 1996-03-30 1996-03-30 Three state output circuit

Publications (2)

Publication Number Publication Date
KR970068167A true KR970068167A (en) 1997-10-13
KR0157955B1 KR0157955B1 (en) 1999-03-20

Family

ID=19454667

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960009549A KR0157955B1 (en) 1996-03-30 1996-03-30 Three state output circuit

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KR (1) KR0157955B1 (en)

Also Published As

Publication number Publication date
KR0157955B1 (en) 1999-03-20

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