AU2001245520A1 - Vliw computer processing architecture having a scalable number of register files - Google Patents
Vliw computer processing architecture having a scalable number of register filesInfo
- Publication number
- AU2001245520A1 AU2001245520A1 AU2001245520A AU4552001A AU2001245520A1 AU 2001245520 A1 AU2001245520 A1 AU 2001245520A1 AU 2001245520 A AU2001245520 A AU 2001245520A AU 4552001 A AU4552001 A AU 4552001A AU 2001245520 A1 AU2001245520 A1 AU 2001245520A1
- Authority
- AU
- Australia
- Prior art keywords
- computer processing
- register files
- processing architecture
- scalable number
- vliw computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
- G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18790200P | 2000-03-08 | 2000-03-08 | |
US60187902 | 2000-03-08 | ||
PCT/US2001/007387 WO2001067234A2 (en) | 2000-03-08 | 2001-03-08 | Vliw computer processing architecture having a scalable number of register files |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001245520A1 true AU2001245520A1 (en) | 2001-09-17 |
Family
ID=22690957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001245520A Abandoned AU2001245520A1 (en) | 2000-03-08 | 2001-03-08 | Vliw computer processing architecture having a scalable number of register files |
Country Status (5)
Country | Link |
---|---|
US (2) | US6988181B2 (en) |
EP (1) | EP1261910A2 (en) |
AU (1) | AU2001245520A1 (en) |
HK (1) | HK1048536A1 (en) |
WO (1) | WO2001067234A2 (en) |
Families Citing this family (42)
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EP1346282A1 (en) | 2000-12-11 | 2003-09-24 | Koninklijke Philips Electronics N.V. | Signal processing device and method for supplying a signal processing result to a plurality of registers |
AU2002252173A1 (en) * | 2001-02-28 | 2002-09-12 | Brecis Communications Corporation | A security system with an intelligent dma controller |
US7233998B2 (en) * | 2001-03-22 | 2007-06-19 | Sony Computer Entertainment Inc. | Computer architecture and software cells for broadband networks |
US7203817B2 (en) * | 2001-09-24 | 2007-04-10 | Broadcom Corporation | Power consumption reduction in a pipeline by stalling instruction issue on a load miss |
KR100947446B1 (en) * | 2002-03-28 | 2010-03-11 | 엔엑스피 비 브이 | Vliw processor |
US7337334B2 (en) * | 2003-02-14 | 2008-02-26 | International Business Machines Corporation | Network processor power management |
DE602004025691D1 (en) | 2003-04-15 | 2010-04-08 | Koninkl Philips Electronics Nv | COMPUTER SYSTEM WITH PARALLELITY ON COMMAND AND WIRE LEVEL |
JP5068529B2 (en) * | 2003-04-29 | 2012-11-07 | シリコン ハイブ ビー・ヴィー | Zero-overhead branching and looping in time-stationary processors |
US20050251649A1 (en) * | 2004-04-23 | 2005-11-10 | Sony Computer Entertainment Inc. | Methods and apparatus for address map optimization on a multi-scalar extension |
US7890735B2 (en) * | 2004-08-30 | 2011-02-15 | Texas Instruments Incorporated | Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture |
JP2007164286A (en) * | 2005-12-09 | 2007-06-28 | Sony Corp | Information signal processor, functional block and method for controlling functional block |
US7669041B2 (en) * | 2006-10-06 | 2010-02-23 | Stream Processors, Inc. | Instruction-parallel processor with zero-performance-overhead operand copy |
JP5126226B2 (en) * | 2007-05-17 | 2013-01-23 | 富士通株式会社 | Arithmetic unit, processor and processor architecture |
US8473818B2 (en) * | 2009-10-12 | 2013-06-25 | Empire Technology Development Llc | Reliable communications in on-chip networks |
US8788766B2 (en) * | 2010-02-18 | 2014-07-22 | Oracle America, Inc. | Software-accessible hardware support for determining set membership |
CN110083494B (en) * | 2011-12-30 | 2023-07-25 | 英特尔公司 | Method and apparatus for managing hardware errors in a multi-core environment |
US9207944B1 (en) * | 2013-03-15 | 2015-12-08 | Google Inc. | Doubling thread resources in a processor |
US9665372B2 (en) | 2014-05-12 | 2017-05-30 | International Business Machines Corporation | Parallel slice processor with dynamic instruction stream mapping |
US9672043B2 (en) | 2014-05-12 | 2017-06-06 | International Business Machines Corporation | Processing of multiple instruction streams in a parallel slice processor |
US9760375B2 (en) | 2014-09-09 | 2017-09-12 | International Business Machines Corporation | Register files for storing data operated on by instructions of multiple widths |
US9720696B2 (en) | 2014-09-30 | 2017-08-01 | International Business Machines Corporation | Independent mapping of threads |
US9977678B2 (en) | 2015-01-12 | 2018-05-22 | International Business Machines Corporation | Reconfigurable parallel execution and load-store slice processor |
US10133576B2 (en) | 2015-01-13 | 2018-11-20 | International Business Machines Corporation | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries |
US10133581B2 (en) | 2015-01-13 | 2018-11-20 | International Business Machines Corporation | Linkable issue queue parallel execution slice for a processor |
US9983875B2 (en) | 2016-03-04 | 2018-05-29 | International Business Machines Corporation | Operation of a multi-slice processor preventing early dependent instruction wakeup |
US10037211B2 (en) | 2016-03-22 | 2018-07-31 | International Business Machines Corporation | Operation of a multi-slice processor with an expanded merge fetching queue |
US10346174B2 (en) | 2016-03-24 | 2019-07-09 | International Business Machines Corporation | Operation of a multi-slice processor with dynamic canceling of partial loads |
US10761854B2 (en) | 2016-04-19 | 2020-09-01 | International Business Machines Corporation | Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor |
US10037229B2 (en) | 2016-05-11 | 2018-07-31 | International Business Machines Corporation | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions |
US9934033B2 (en) | 2016-06-13 | 2018-04-03 | International Business Machines Corporation | Operation of a multi-slice processor implementing simultaneous two-target loads and stores |
US10042647B2 (en) | 2016-06-27 | 2018-08-07 | International Business Machines Corporation | Managing a divided load reorder queue |
US10318419B2 (en) | 2016-08-08 | 2019-06-11 | International Business Machines Corporation | Flush avoidance in a load store unit |
US11868804B1 (en) | 2019-11-18 | 2024-01-09 | Groq, Inc. | Processor instruction dispatch configuration |
US11243880B1 (en) | 2017-09-15 | 2022-02-08 | Groq, Inc. | Processor architecture |
US11360934B1 (en) | 2017-09-15 | 2022-06-14 | Groq, Inc. | Tensor streaming processor architecture |
US11114138B2 (en) | 2017-09-15 | 2021-09-07 | Groq, Inc. | Data structures with multiple read ports |
US11170307B1 (en) | 2017-09-21 | 2021-11-09 | Groq, Inc. | Predictive model compiler for generating a statically scheduled binary with known resource constraints |
US11301546B2 (en) | 2018-11-19 | 2022-04-12 | Groq, Inc. | Spatial locality transform of matrices |
TWI719433B (en) * | 2019-03-22 | 2021-02-21 | 美商葛如克公司 | Data structures with multiple read ports, processor, and method for data structures with multiple read ports |
TWI751882B (en) * | 2019-03-22 | 2022-01-01 | 美商葛如克公司 | Data structures with multiple read ports, processor, and method for data structures with multiple read ports |
US11907126B2 (en) * | 2020-09-25 | 2024-02-20 | Advanced Micro Devices, Inc. | Processor with multiple op cache pipelines |
US20220100519A1 (en) * | 2020-09-25 | 2022-03-31 | Advanced Micro Devices, Inc. | Processor with multiple fetch and decode pipelines |
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-
2001
- 2001-03-08 AU AU2001245520A patent/AU2001245520A1/en not_active Abandoned
- 2001-03-08 US US09/802,289 patent/US6988181B2/en not_active Expired - Lifetime
- 2001-03-08 EP EP01918442A patent/EP1261910A2/en not_active Withdrawn
- 2001-03-08 WO PCT/US2001/007387 patent/WO2001067234A2/en not_active Application Discontinuation
- 2001-03-08 US US09/802,108 patent/US7020763B2/en not_active Expired - Lifetime
-
2003
- 2003-01-23 HK HK03100609.0A patent/HK1048536A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
WO2001067234A2 (en) | 2001-09-13 |
WO2001067234A3 (en) | 2002-05-10 |
EP1261910A2 (en) | 2002-12-04 |
US20020023201A1 (en) | 2002-02-21 |
US7020763B2 (en) | 2006-03-28 |
US6988181B2 (en) | 2006-01-17 |
US20020049892A1 (en) | 2002-04-25 |
HK1048536A1 (en) | 2003-04-04 |
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