TWI719433B - Data structures with multiple read ports, processor, and method for data structures with multiple read ports - Google Patents

Abstract

A memory structure having 2^m read ports allowing for concurrent access to n data entries can be constructed using three memory structures each having 2^m-1 read ports. The three memory structures include two structures providing access to half of the n data entries, and a difference structure providing access to difference data between the halves of the n data entries. Each pair of the 2^m ports is connected to a respective port of each of the 2^m-1-port data structures, such that each port of the part can access data entries of a first half of the n data entries either by accessing the structure storing that half directly, or by accessing both the difference structure and the structure containing the second half to reconstruct the data entries of the first half, thus allowing for a pair of ports to concurrently access any of the stored data entries in parallel.

Description

Data structure with multiple read ports, processor, and method for data structure with multiple read ports

The present invention generally relates to the storage of data structures, and more specifically, the present invention relates to the storage of data structures with multiple read ports.

Data structures (such as look-up tables) can be used in many applications to perform a function on the received input data. For example, an arithmetic logic unit (ALU) can perform an operation on the received input value by looking up a received input value in a lookup table and returning a corresponding output value.

In some cases (such as in single instruction multiple data (SIMD) applications), it may be desirable to be able to perform the same operation on different sets of input data in parallel. Therefore, multiple ALUs or other circuits need to be able to access the data contained in the look-up table in parallel.

A memory structure with multiple read ports can be used to allow multiple ALUs or other processing devices to access a common data structure (such as a look-up table) in parallel. A plurality of memory structures with fewer read ports can be used to construct the memory structure.

Each can be used with three memory structure 2 ^m-1 number of read ports (e.g. sub-structures) allow simultaneous access to construct having a read port of 2 ^m n number of data entries, one memory structure. The three memory structures include: a first structure that provides access to the first half (n/2 input items) of one of the n data entry items; a second structure that provides access to the n data entry items Access to the second half (n/2 input items) of one of the data input items; and a difference structure that provides the first half and the second half (n/2 input items) of the n data input items Item) access to the difference data. Each of the 2 ^m ports can be connected to a respective port of each of the 2 ^m-1 port data structures, so that one port can be accessed by accessing the first structure or by accessing the differential structure and the The second structure both come from the first half of the access data of the n data entries to reconstruct the data stored by the first structure. Similarly, a port can be reconstructed from the second half of the access data from the n data entries by accessing the second structure or by accessing both the difference structure and the first structure. The data stored in the structure.

Therefore, three 1-port memory structures each storing n/2 data input items can be used to construct a 2-port memory structure for accessing n data input items. Similarly, multiple 1-port memory structures storing a total of (3/2) ^{m *n input items can be used to construct a 2 m-} port memory structure for accessing one of n data input items.

100: Multi-port memory structure

102: Arithmetic Logic Unit (ALU)

104: Read port

200:1 port memory structure

205: read port

300: 2-port memory structure

305A: The first 1-port memory structure/lower structure

305B: second 1-port memory structure/upper structure

310: The third port 1 structure/differential structure

315: Access Circuit

320: access circuit

320A: Lower reading port

320B: Upper reading port

325: Multiplexer (MUX)

325A: Down MUX

325B: Upper MUX

330: Difference Circuit

330A: First difference circuit

330B: Second difference circuit

335: Conflict Control Circuit

400: 4-port memory structure

405A: Lower 2-port memory structure/first 2-port memory structure

405B: Upper 2-port memory structure/Second 2-port memory structure

410: Differential 2-port memory structure/third 2-port memory structure

415A: Lower structure

415B: Upper structure

415C: Differential structure

420A: Lower structure

420B: Upper structure

420C: Differential structure

425A: Lower structure

425B: Upper structure

425C: Differential structure

430: Sub-Access Circuit

430A: Sub-access circuit

430B: Sub-access circuit

430C: Sub-access circuit

435: access circuit

435A: The first access circuit

435B: second access circuit

440A: Read port

440B: Read port

440C: Read port

440D: Read port

502: first method

504: second method

506: third method

508: The Fourth Method

600: 2 ^m port memory structure

605A: Lower structure/lower table

605B: Upper structure/Upper table

610: Difference structure / difference sub-table

615: Access Circuit

615-1 to 615-2 ^m-1 : Access circuit

625: read port

625-1 to 625-2 ^m-1 : read port

FIG. 1 shows a block diagram of a processor having a memory structure with a plurality of read ports according to some embodiments.

FIG. 2 shows a memory structure with a single read port according to some embodiments.

FIG. 3 shows a memory structure with two read ports according to some embodiments.

FIG. 4 shows a diagram of a 4-port structure that can be assembled using three different 2-port structures according to some embodiments.

FIG. 5 shows a diagram of how the ports of the 4-port structure can access any data input items of the structure in parallel.

FIG. 6 shows a structure with 2 ^m read ports ^{constructed from three 2 m-1 port structures according to some embodiments.}

The drawings depict embodiments of the invention for illustration only. Those skilled in the art should easily recognize from the following description that alternative embodiments of the structure and method described herein can be used without departing from the principles of the invention described herein or Fitch.

The drawings and the following description are about preferred embodiments for illustration only. It should be noted that it will be easy to recognize from the following discussion that alternative embodiments of the structures and methods disclosed herein are feasible alternatives that can be adopted without departing from the claimed principles.

A data structure (such as a lookup table) can be used by an arithmetic logic unit (ALU) or other circuit to perform an operation on the received input value. In many parallel processing applications (such as single instruction multiple data (SIMD) applications), multiple ALUs need to access the data structure in parallel. Therefore, it is desirable that the data structure be implemented on a memory structure (such as a random access memory (RAM) or read-only memory (ROM)) having multiple read ports. In addition, although the present invention mainly relates to the ALU reading data from the data structure through one or more read ports, in other embodiments, any other types of circuits or consumers can read data from the data structure through one or more read ports. Read the data.

FIG. 1 shows a block diagram of a processor including a memory structure having a plurality of read ports according to some embodiments. The processor may be an integrated circuit (IC) device. In some embodiments, the processor is a processor dedicated to tensor processing. The processor includes a multi-port memory structure 100 and a plurality of ALUs 102. The multi-port memory structure 100 includes a dynamic random access memory (DRAM) cell or another type of memory that stores a data structure (such as a look-up table) accessed by a plurality of ALUs 102. In some embodiments, the data structure is associated with a function, and the function input value is mapped to the function output value. For example, the data structure implements one of a machine learning model Activation functions, such as rectified linear unit (RELU) functions, binary step functions, arctangent functions, or other functions.

The ALU 102 may be part of a SIMD or other parallel processor, where each ALU 102 is configured to perform the same arithmetic operation on different sets of input data. For example, each ALU 102 receives a respective input data set, and performs one or more searches on the data structure stored in the memory structure 100 to generate a respective output data set based on the function associated with the data structure. In order for the ALU 102 to operate in parallel, multiple ALUs 102 need to be able to access the data structure on the memory structure 100 at the same time. For example, FIG. 1 shows a memory structure 100 with four read ports 104, each of which is connected to one of four different ALUs 102. In one embodiment, each read port has its own dedicated address bus and its own dedicated data bus. The ALU reads data through a read port by providing an address to the address bus, and the memory structure 100 returns data from the data structure located at the address. As used herein, "simultaneously" may refer to during a common time period (for example, a clock cycle). For example, each of a plurality of ALUs can transmit a read request to the memory structure 100 during a specific clock cycle, where the transmitted read requests can be regarded as simultaneous with each other.

In some embodiments, a memory structure with fewer read ports can be used to construct a memory structure with multiple read ports (such as the memory structure 100). For example, the memory structure 100 can be constructed by a plurality of memory structures each having a single read port. FIG. 2 shows a memory structure with a single read port according to some embodiments. The memory structure 200 stores a plurality of data input items (for example, input items [0] to [n-1], where n includes an integer value of 2 or greater). Because the memory structure 200 only has a single read port 205, only a single ALU can access the data contained in the memory structure 200 at a time.

An exemplary method of allowing multiple ALUs to access data of the memory structure 200 in parallel is to copy data across multiple single read port memory structures (for example, input items [0] to [n-1]). For example, the data of structure 200 can be copied across a second single read port memory structure to construct a combined memory structure with two read ports, each of which can be independently stored by a different ALU Taken to provide any access to the data in the original structure. However, this configuration also doubles the amount of memory required to store data, because each of the input items [0] to [n-1] will be copied across two separate memory structures. Using this type of configuration, in order to build a ^{memory structure with n input items that can be accessed through 2 m} read ports, a total of n*2 ^m input items will need to be stored, where m includes a positive integer value .

2-port memory structure

FIG. 3 shows a memory structure with two read ports according to some embodiments. As shown in Figure 3, one of the n input items (for example, input items [0] to [n-1]) that allows parallel access to data, the 2-port memory structure 300 consists of three 1-port memories Structure construction. Each 1-port memory structure contains a table or other data structures that store half the number of data input items (for example, n/2 input items) of the original data structure. Therefore, compared with the original 1-port memory structure (such as the 1-port structure 200 shown in FIG. 2), the 2-port memory structure 300 will only need to store more than 50% of the input items, while still allowing reading through two Any one of the ports can access all n input items at the same time.

The 2-port memory structure 300 includes a first 1-port memory structure 305A that stores data entry items [0] to [n-1] and a first half table and a first 1-port memory structure 305A that stores data entry items [0] to [n -1] One second half one table one second 1-port memory structure 305B. For ease of explanation, the first half of the data entry can also be referred to as the "lower" half (e.g. entry [0] to [n/2-1]), and the second half can also be referred to as the "upper" half (e.g. Enter items [n/2] to [n-1]). Thus, the first structure 305A can be referred to as the "lower structure", and the second structure 305B can be referred to as the "upper structure".

In addition to the lower structure 305A and the upper structure 305B, the 2-port structure 300 further includes Including storing one of the n/2 input items, the third 1-port structure 310 (hereinafter referred to as the "difference structure"), each of these input items indicates whether the corresponding input item of the lower structure and the corresponding input item of the upper structure has a difference. For example, the difference structure can store the difference between the input item [0] of the lower structure and the input item [n/2] of the upper structure, the difference between the input item [0] and [n/2+1], etc.的input item. Any function can be used to determine the difference. The function allows only the value of the corresponding difference and the data entry in the lower or upper half to determine the value of one of the data entries in the other half. For example, in some embodiments, one of the corresponding input items of the lower structure and the upper structure is mutually exclusive or (XOR) to generate an input item in the difference structure. Therefore, without access to the lower structure, the corresponding upper half of the data entry and XOR value can be used to determine the value of a specific data entry in the lower half. In other embodiments, a reversible function other than XOR may be used to calculate the difference input.

The access circuit 315 includes mapping the read ports of the lower structure 305A, the upper structure 305B, and the differential structure 310 to one of two different read ports 320A and 320B (these can be referred to as the lower read port and the upper read port, respectively) Circuit. Each read port 320 is configured to receive a read request specifying the read address of one or more input items to be read. For each read port 320, the access circuit 315 includes a multiplexer (MUX) 325 and a difference calculation circuit 330. Each difference calculation circuit 330 is configured to receive data of a corresponding input item from one of the difference structure 310 and the lower structure 305A or the upper structure 305B to calculate the value of a corresponding input item from the remaining upper structure 305B or the lower structure 305A (such as borrowing By implementing an XOR operation or other reversible function). For example, one of the corresponding input items XOR of the lower structure 305A and the difference structure 310 (for example, input item [0] and input item ([0]XOR[n/2])) can be used to determine any input item in the upper structure 305B ( For example, the entry [n/2]). Therefore, a specific read port can provide data corresponding to the input items of the upper structure 305B by combining the data retrieved from the lower structure 305A and the difference structure 310, even if the upper structure 305B is unavailable (for example, due to other reads Port access). Similarly, when the lower structure 305A is not available, you can access the upper structure 305B and the difference The structure 310 determines the data entry of the lower structure 305A.

In some embodiments, the difference circuit 330 includes: a first difference circuit 330A, which is configured to use the lower structure 305A and the difference structure 310 to determine the input value of the upper structure 305B; and a second difference circuit 330B, which It is configured to use the upper structure 305B and the difference structure 310 to determine the input value of the lower structure 305A. The first difference circuit 330A and the second difference circuit 330B may be referred to as a lower difference circuit and an upper difference circuit, respectively.

MUX 325 includes a lower MUX 325A and an upper MUX 325B, each of which is configured to be in the lower structure 305A (for a read request from the lower half of the stored input item), the upper structure 305A (for a read request) When requesting an address from the upper half of the stored input item) and the output of one of the difference circuit 330A or 330B, the selected output is selected and provided to a respective read port 320A/B. For example, the lower read port 320A receives an output of the lower MUX 325A connected to the difference circuit 330A, and the upper read port 320B receives an output of the upper MUX 325B connected to the difference circuit 330B.

In some embodiments, a conflict control circuit 335 uses a priority scheme to determine how each of the read ports 320A and 320B can access the data entries stored by the structures 305A, 305B, and 310. The conflict control circuit 335 is configured to receive an address from the read port corresponding to the received read request, and by controlling the structure selection of the MUX 325A/B to receive data from each read port 320A/B to perform any simultaneous Resolve conflicts between received requests.

For example, as discussed above, the read port 320 can be labeled as a lower read port 320A and an upper read port 320B. The lower reading port 320A has a "priority" over the lower structure 305A. Therefore, the conflict control circuit 335 configures the MUX 325A to directly read all requests for the input items in the lower structure 305A from the lower structure 305A through the lower read port 320A. Similarly, the upper read port 320B has a "priority" to the upper structure 305B so as to use the upper read port 320B from the upper structure 305B directly reads all requests for the input items in the above structure 305B. In addition, the conflict control circuit 335 can configure the MUX 325A/B so that whenever each read port 320A/B does not receive a simultaneous read request to read data from the same structure, the other read port is free from it. The lower structure 305A/upper structure 305B with priority is read directly. However, if the lower reading port 320A and the upper reading port 320B both receive the reading of one or more input items from the upper structure 305B, the conflict control circuit 335 configures the MUX 325A so that the lower reading port 320A Instead of reading from the output of the difference calculation circuit 330A, it uses the corresponding input item of the lower structure 305A and the difference structure 310 to determine the value of the request input item of the upper structure 305B. Similarly, if the lower read port 320A and the upper read port 320B simultaneously receive a request to read one or more input items from the lower structure 305A, the conflict control circuit 335 configures the MUX 325B to cause the upper read port 320B to be different The output of the calculation circuit 330B is read.

Although FIG. 3 shows a specific access circuit configuration, it should be understood that in other embodiments, other access circuit configurations are possible. For example, in some embodiments, the read port 320A or 320B can use the relative structure and the difference structure to read the data entry of the lower structure or the upper structure. In some embodiments, an access circuit can be configured to map a plurality of memory structures to more than two ports.

2 ^m Port memory structure

The construction of the 2-port memory structure using the 1-port memory structure discussed above can be extrapolated to assemble a structure with an additional number of available read ports (for example, 2 ^m read ports). FIG. 4 shows a diagram of a 4-port memory structure that can be assembled using three different 2-port memory structures according to some embodiments. The 4-port memory structure 400 is constructed by three 2-port memory structures (including a lower 2-port memory structure 405A, an upper 2-port memory structure 405B, and a differential 2-port memory structure 410). Each of the 2-port memory structures 405A, 405B, and 410 can be constructed in a manner similar to the 2-port memory structure 300 shown in FIG. 3 (for example, constructed by three 1-port memory structures).

For the purpose of discussion, the data input items stored in the table implemented on the 4-port memory structure 400 are divided into data subsets "A", "B", "C" and "D", each of which corresponds to the 4-port structure 400 1/4 of all data input items.

The first 2-port memory structure 405A includes three 1-port memory structures, including a lower structure 415A for storing a table containing a data subset "A", and a lower structure for storing a table containing a data subset "B". The structure 415B and the difference between the storage instruction data subset "A" and "B" (for example, "A♁B") are a table of a difference structure 415C. Similarly, the second 2-port memory structure 405B includes a lower structure 420A for storing a table containing a data subset "C", an upper structure 420B for storing a table containing a data subset "D", and a storing instruction data subset The difference between "C" and "D" (for example, "C♁D") represents a difference structure 420C. Therefore, the first 2-port memory structure 405A and the second 2-port memory structure 405B can serve as a 2-port lower structure and a 2-port upper structure of the 4-port memory structure 400. The third two-port memory structure 410 serves as a two-port differential structure between the first two-port memory structure 405A and the second two-port memory structure 405B, which includes the storage instruction data subsets "A" and "C". The difference between (e.g. "A♁C") is one of the lower structure 425A, and the difference between the storage instruction data subset "B" and "D" (e.g. "B♁D") is one of the upper structure 425B and storage indicate the difference between all four data subsets (for example, "(A♁C)♁(B♁D)") a table of a difference structure 425C. As shown in Figure 4, an XOR operation can be used to determine the difference between data subsets.

Each of the 2-port memory structures 405A, 405B, and 410 also includes a respective access circuit 430 (hereinafter referred to as sub-access circuit 430 (for example, sub-access circuit 430A, 430B, and 430C)), and its structure can be substantially similar to The access circuit 315 shown in FIG. 3.

Each port of each of the three sub-access circuits 430 is connected to an access circuit 435. For example, the first access circuit 435A is connected to the lower read port of each sub-access circuit 430, and the second access circuit 435B is connected to the upper read port of each sub-access circuit 430. Each access circuit 435A may have a structure substantially similar to the access circuit 315 of FIG. 3. Since each access circuit 435 has two read ports, the 4-port memory structure 400 has a total of four read ports 440A, 440B, 440C, and 440D, each of which can access the data subsets "A" and " Any of "B", "C" and "D".

Depicted in FIG. 4, for providing the n 4 data ports 400 access the memory structure of the entry may be used to store each one of the tables contains nine of n / 4 th Data entry ⁽² or 3 ) A 1-port memory structure, or as three 2-port memory structures each storing a table containing a total of (3n/4) data entry items. Therefore, the 4-port memory structure 400 stores a table containing a total of 9n/4 data entry items. Generally speaking, using the construction scheme discussed above, a total of (3/2) ^m *n input items can be stored in the upper sub-structure, lower sub-structure and difference sub-structure to construct a configured configuration to provide A memory structure ^{of 2 m} ports for parallel access of n data input items. In contrast, only one copy port memory structure 1 to provide additional ports would need to store ports of 2 ^m 2 ^m * n number of entries.

FIG. 5 shows a diagram of how the ports of the 4-port memory structure can concurrently access any data input items stored by the structure. As discussed above, the data input items stored by the 4-port memory structure can be divided into four data subsets: "A", "B", "C" and "D", each of which can be used as A table is stored on a single 1-port memory structure. In addition, the 4-port structure contains five additional 1-port structures that store the table indicating the difference between one or more pairs of data subsets (for example, the four structures that store the difference between a pair of data subsets and the storage of two pairs of data subsets). A structure of the set of differences). Therefore, nine 1-port memory structures (for example, grouped into three 2-port memory structures, as shown in FIG. 4) are used to assemble a 4-port memory structure.

Using the above construction, a read port of a 4-port memory structure can use one of four different methods to access a specific data entry (for example, a data entry of data subset "A") to allow memory All four read ports of the structure access data input items in parallel. Using the first method 502, a read port can access the data subset "A" by storing the 1-port memory structure of the table containing the data subset "A" (for example, the structure 415A shown in FIG. 4). On the other hand, the remaining methods 504, 506, and 508 need to reconstruct the data subset "A" by accessing a plurality of other memory structures. For example, the read port can use the second method 504 to access the memory that stores the table containing the data subset "B" (structure 41B) and the difference between the data subset "A" and "B" (structure 415C) Structure to determine the input items of the data subset "A". Alternatively, using the third method 506, the port can access and store the memory structure containing the data subset "C" (structure 420A) and the table of the difference between "A" and "C" (structure 425A) to determine the data Input items of subset "A". Using the fourth method 508, the port access storage contains the data subset "D" (structure 420B), the difference between "C" and "D" (structure 420C), and the difference between "B" and "D" ( The memory structure of the table of structure 425B) and the difference between all four data subsets (structure 425C) is used to determine the input items of data subset "A". It is also possible to use one of four different methods to determine each of the remaining data subsets "B", "C" and "D" in a similar manner. Therefore, any data from any of the data subsets can be accessed or determined in parallel at each of the four read ports.

The above technology and construction can be further extrapolated to construct a ^{memory structure with 2 m} read ports. FIG. 6 shows a memory structure with 2 ^{m read ports constructed from three 2 m-1 port structures according to some embodiments. Three 2 m-1} port memory structures including a lower structure 605A, an upper structure 605B, and a differential structure 610 ^{are used to construct each 2 m} port memory structure for providing access to n data input items. Each 2 ^m-1 port memory structure provides access to n/2 data input items. For example, the lower half of n data input items are stored in the lower structure 605A, the upper half of n data input items are stored in the upper structure 605B, and the difference structure 610 stores the corresponding lower half of the input items and the upper half of the input The difference between items.

^{Each of the 2 m-1} ports of the 2 ^m-1 port memory structure is mapped to an access circuit 615 (for example, the access circuits 615-1 to 615-2 ^m-1 ). For example, each one of those three 2 ^m-1 th memory structure of the first port is mapped to a first access port circuit 615-1, each one of those three port 2 ^m-1 memory structure of th The two ports are mapped to a second access circuit 615-2 and so on, up to the access circuit 615-2 ^m-1 .

Each access circuit 615 contains two reading ports 625 (for example, a lower reading port and an upper reading port 625-1 and 625-2...625-(2 ^m-1 -1) and 625-2 ^m- 1)), each of them can directly access the 2 ^m-1 port lower structure 605A and the 2 ^m-1 port upper structure 605B or use the difference structure 610 and the relative structure to determine the value of the data input item of the lower structure or the upper structure. For example, each access circuit can be configured so that its respective lower read port can always directly access the lower sub-table 605A, but when the respective upper read port needs to simultaneously access the upper sub-table 605B, the lower sub-table 605A and the difference sub-table 605A are used. Table 610 determines the value of the entry in the upper sub-table 605B. Similarly, the upper read port can always access the upper sub-table 605B, but when the lower read port accesses the lower sub-table 605A at the same time, the upper sub-table 605B and the difference sub-table 610 are used to determine the value of the entry in the lower sub-table 605A .

Therefore, as shown in FIG. 6, the 2 ^{m- port memory structure will include 2 m-1} access circuits mapped to each of the three 2 ^m-1 port memory structures. Since each access circuit 615 contains 2 ports, a total of 2 ^m ports are available. This allows a 2 ^m port structure to be constructed using (3/2) ^m *n input items.

Although the technology described herein mainly discusses the use of a 1-port memory structure to construct a memory structure with multiple read ports, it should be understood that in other embodiments, there are more than one read port (for example, two read ports). , 3 read ports, etc.) memory structure can be used to construct a memory structure with additional read ports. For example, three memory structures each with k read ports It can be used to construct a memory structure with up to 2k read ports using the above configuration.

In addition, the constructed memory structure need not be limited to 2 ^m ports. For example, if a particular level of the memory structure contains a port number that is not a power of 2, then a subsequent level may also have a port number that is not a power of 2 (for example, three 3-port memory structures can be used to construct A 6-port memory structure). In addition, fewer access circuits can be used at a given level to reduce the total number of available read ports. For example, referring to FIG. 6, less than (m-1) access circuits can be used, so that not each ^{port of each 2 m-1} port substructure is mapped to an access circuit 615, resulting in less than 2 ^m total read ports .

Although the above example illustrates the use of two sub-structures (such as the lower half and the upper half) of the stored data subset to construct the various levels of a multi-access memory structure, it should be understood that in other embodiments, A different number of substructures can be used. For example, in some embodiments, the data entry items can be divided between three substructures and a difference substructure. A different operation (such as addition mod 3) can be used to replace the difference corresponding to an XOR operation. In some embodiments, an access circuit can be configured to connect multiple sub-structures to more than two ports and control access to multiple sub-structures.

Write data

^{A multi-port memory structure (such as the 2 m-} port memory structure 600 described in FIG. 6) constructed by a plurality of constituent memory structures (such as the 1-port memory structure 200 described in FIG. 2) can be It is considered to include multiple levels. ^{For example, a 2 m-} port memory structure constructed from a plurality of 1-port memory structures may include m levels, and each level includes ^{3 k memory structures each with 2 mk} read ports, where k indicates a level and Corresponds to an integer between 1 and m. For example, referring to the 4-port memory structure 400 shown in FIG. 4, the memory structure 400 has a k=1 level with one of three 2-port memory structures and a k=2 with one of nine 1-port memory structures Level.

When writing data into a 2 ^m- port memory structure, a recursive writing process is used to make the data to be written reflect in all levels of the structure. For example, referring to the configuration shown in Figure 4, in order to write new data into a specific data subset (for example, data subset "B"), it is necessary to write data to the 2-port lower structure 405A and the difference structure 410. In the 2-port lower structure 405A, write data to the upper structure 415B (the table containing the stored data subset "B"). In addition, the data of the difference structure 415C (stored (A♁B)) is also recalculated. In addition, in the 2-port differential structure 410, the data in the upper structure 425B (storage (B♁D)) and the differential structure 425C (storage (A♁C)♁(B♁D)) also need to be recalculated.

Additional configuration information

The above description of the embodiments of the invention has been presented for illustration; it is not intended to be exhaustive or to limit the invention to the precise form disclosed. Those who are familiar with the relevant technology should understand that many modifications and changes can be made based on the above disclosure.

Some parts of this description describe the embodiments of the present invention in terms of algorithms and symbolic representations of operations on information. These algorithm descriptions and representations are often used by those who are familiar with data processing technology to effectively convey the essence of their work to other people who are familiar with the technology. When described in terms of function, calculation or logic, these operations should be understood as being implemented by computer programs or equivalent circuits, microcode or the like. In addition, it is sometimes proved that it is convenient to refer to such configurations of operations as modules without loss of generality. The described operations and their associated modules can be embodied in software, firmware, hardware, or any combination thereof.

One or more hardware or software modules can be used alone or in combination with other devices to execute or implement any of the steps, operations, or procedures described herein. In one embodiment, a software module is implemented using a computer program product including a computer readable medium containing computer program code, and the computer program code can be executed by a computer processor to perform the described steps, operations, or procedures Any or all of.

The embodiments of the present invention may also relate to a device for performing the operations herein. The device may be specially constructed for the required purpose, and/or it may include a general-purpose computing device that is selectively activated or reconfigured by a computer program stored in the computer. This computer program can be stored in a non-transitory, tangible computer-readable storage medium or any type of medium suitable for storing electronic instructions (which can be coupled to a computer system bus). In addition, any computing system mentioned in this specification may include a single processor or may be an architecture that uses multiple processors designed to increase computing power.

The embodiments of the present invention may also be related to a product produced by a calculation program described herein. Such a product may include information derived from a computing process, where the information is stored on a non-transitory, tangible computer-readable storage medium and may include any embodiment of a computer program product or other combination of data described herein.

Finally, the terms used in this specification have been chosen mainly for readability and teaching, and they have not been chosen to delimit or limit the subject matter of the present invention. Therefore, the scope of the present invention is not intended to be limited to [implementations], but to any claims issued on an application based on this. Therefore, the disclosure of the embodiments is intended to illustrate rather than limit the scope of the present invention described in the scope of the following patent applications.

100: Multi-port memory structure

102: Arithmetic Logic Unit (ALU)

104: Read port

Claims (15)

A memory structure comprising: a first memory substructure configured to store a first subset of data; a second memory substructure configured to store a second subset of data Set; a third memory substructure configured to store difference data corresponding to the first subset of data and the second subset of data; at least one first read port and a second read Ports, each of which is configured to receive a read request for the first subset of data read from the first memory substructure or the second subset of data read from the second memory substructure; And an access circuit connected to the first memory substructure, the second memory substructure, and the third memory substructure to control access by the first read port and the second read port The first memory substructure, the second memory substructure, and the third memory substructure, and the access circuit is configured to respond to the first read port and the second read port Both receive read requests from the second subset of data stored on the second memory substructure during a first time period, and by combining the read requests from the second memory substructure The requested data is provided to the second read port to prioritize the second read port to satisfy the read request from the second read port, and use the data stored on the first memory substructure The first subset and the corresponding part of the difference data stored on the third memory substructure to reconstruct a part of the second subset of data to satisfy the read request from the first read port, and Responding to both the first read port and the second read port during a second time period Receive a read request from the first subset read of data stored on the first memory substructure, and by providing the requested data from the first memory substructure to the first read Fetch ports to prioritize the first read port to satisfy the read request from the first read port, and use the second subset of data stored on the second memory substructure and store in the The corresponding part of the difference data on the third memory substructure reconstructs a part of the first subset of data to satisfy the read request from the second read port. Such as the memory structure of claim 1, wherein the reconstructed part of the second subset of data is read through the first read port, and the first sub-set of the second subset of data read through the second read port Set the reconstruction part. Such as the memory structure of request 2, in which the access circuit is configured to respond to the read request of the second subset of the data received from the second read port during a same clock cycle And allow the first read port to read request data from the second memory substructure of the second subset of stored data, and respond to data not received from the first read port during a same clock cycle The read request for the first subset of data to read allows the second read port to read the requested data from the first memory substructure of the first subset of stored data. For example, the memory structure of request 1, wherein the difference data includes the "mutual exclusive OR (XOR)" value between the corresponding parts of the first subset of data and the second subset of data. For example, the memory structure of claim 1, wherein each of the first memory substructure, the second memory substructure, and the third memory substructure contains 2 ^m-1 read ports, where m is one A positive integer, each of the read ports can read any of the data contained in the respective memory substructure in parallel. Such as the memory structure of claim 5, wherein at least a part ^{of the 2 m-1} read ports of each of the first memory substructure, the second memory substructure, and the third memory substructure are connected To a respective access circuit to control access to the first memory sub-structure, the second memory sub-structure and the third from at least one respective first read port and second read port of the respective access circuit Memory substructure. Such as the memory structure of request 1, in which the first subset and the second subset of data are associated with a function, and the first read port and the second read port are configured to receive in parallel These read requests are part of a single instruction multiple data (SIMD) application. Such as the memory structure of claim 1, wherein the first time period and the second time period correspond to the first clock cycle and the second clock cycle, respectively. A processor comprising: a plurality of arithmetic logic units (ALU), each of which is configured to implement a mathematical function; a memory structure, which stores data representing the output of the mathematical function of different input values, and has A plurality of read ports communicating with the plurality of ALUs, each ALU implements the mathematical function by sending a read request of the part of the stored data through a corresponding read port, the memory structure includes: A first memory, which is used to store a first subset of the data; a second memory, which is used to store a second subset of the data; a third memory, which is used to store representative data Difference data between the first subset and the second subset of data; and an access circuit connected to the first memory, the second memory, and the third memory to control The first memory, the second memory, and the third memory are accessed by the plurality of read ports, and are configured to respond to one of the plurality of read ports, a first read port and a Both second read ports receive read requests from the second subset of the data stored on the second memory during a first time period, and by transferring the read requests from the second memory The requested data is provided to the second read port to prioritize the second read port to satisfy the read request from the second read port, and use the data stored on the first memory The first subset and the corresponding part of the difference data stored on the third memory reconstruct a part of the second subset of data to satisfy the read request from the first read port, and respond to the Both the first read port and the second read port receive read requests read from the first subset of data stored on the first memory during a second time period, and by The requested data from the first memory is provided to the first read port to prioritize the first read port to satisfy the read request from the first read port, and use the data stored in the second The second subset of data on the memory and the corresponding part of the difference data stored on the third memory are used to reconstruct a part of the first subset of data to satisfy the read from the second read port Fetch request. Such as the processor of claim 9, wherein the difference data includes the first subset of data and data The XOR value between the corresponding parts of the second subset. For example, the processor of claim 9, wherein each of the first memory, the second memory, and the third memory contains 2 ^m-1 read ports, where m is a positive integer, and the reads Each port can read any of the data contained in the respective memory in parallel. For example, the processor of claim 11, wherein each of the 2 ^m-1 read ports is connected to a respective access circuit to control access to the first from at least one respective first read port and second read port Memory, the second memory, and the third memory. Such as the processor of claim 9, wherein the plurality of ALUs generate and send read requests in parallel to the memory structure as part of a single instruction multiple data (SIMD) application. A method for reading data from a memory through a plurality of reading ports, which includes: receiving processing by the first ALU and the second ALU at a first arithmetic logic unit (ALU) and a second ALU The input data; the first ALU and the second ALU are based on the received input data to generate respective first read requests and second read requests to retrieve data from a memory structure, the memory structure at least Including: a first substructure, which stores a first subset of data; a second substructure, which stores a second subset of data; and a third substructure, which stores the first subset corresponding to the data The difference data of the second subset of the set and data; During a first time period, the first read request and the second read request are transmitted to an access circuit of the memory structure through the respective first read port and the second read port; The access circuit responds to determining that both the first read request and the second read request are requesting data from the second subset of data, and by passing through the second read port, the data is stored in the The data requested by the second read request of the second subset of data on the second substructure is provided to the second ALU to prioritize the second read port, and stored in the first substructure by using The first subset of data on the structure and the difference data stored on the third substructure will rebuild a request part of the second subset of data and will be requested by the first read via the first read port The requested information is provided to the first ALU. Such as the method of claim 14, wherein the difference data includes an XOR value between corresponding parts of the first subset of data and the second subset of data.

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