AU2001276646A1 - Debugging of multiple data processors - Google Patents

Debugging of multiple data processors

Info

Publication number
AU2001276646A1
AU2001276646A1 AU2001276646A AU7664601A AU2001276646A1 AU 2001276646 A1 AU2001276646 A1 AU 2001276646A1 AU 2001276646 A AU2001276646 A AU 2001276646A AU 7664601 A AU7664601 A AU 7664601A AU 2001276646 A1 AU2001276646 A1 AU 2001276646A1
Authority
AU
Australia
Prior art keywords
debugging
multiple data
data processors
processors
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001276646A
Inventor
Michael A. Byrne
John J. Horrigan
William G. Jacob
Thomas Moore
Martin Jude O'riordan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DELVALLEY Ltd
Original Assignee
DELVALLEY Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DELVALLEY Ltd filed Critical DELVALLEY Ltd
Publication of AU2001276646A1 publication Critical patent/AU2001276646A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2294—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by remote test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
AU2001276646A 2000-07-28 2001-07-30 Debugging of multiple data processors Abandoned AU2001276646A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
IE20000603 2000-07-28
IES2000/0603 2000-07-28
PCT/IE2001/000002 WO2002010994A1 (en) 2000-07-28 2001-01-08 A data processor
AU2001222161 2001-01-08
US29322501P 2001-05-25 2001-05-25
US60/293,225 2001-05-25
PCT/IE2001/000099 WO2002010947A2 (en) 2000-07-28 2001-07-30 Debugging of multiple data processors

Publications (1)

Publication Number Publication Date
AU2001276646A1 true AU2001276646A1 (en) 2002-02-13

Family

ID=11042651

Family Applications (2)

Application Number Title Priority Date Filing Date
AU2001222161A Abandoned AU2001222161A1 (en) 2000-07-28 2001-01-08 A data processor
AU2001276646A Abandoned AU2001276646A1 (en) 2000-07-28 2001-07-30 Debugging of multiple data processors

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AU2001222161A Abandoned AU2001222161A1 (en) 2000-07-28 2001-01-08 A data processor

Country Status (3)

Country Link
US (2) US20020013796A1 (en)
AU (2) AU2001222161A1 (en)
WO (2) WO2002010994A1 (en)

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JP2004164367A (en) * 2002-11-14 2004-06-10 Renesas Technology Corp Multiprocessor system
US20040255195A1 (en) * 2003-06-12 2004-12-16 Larson Thane M. System and method for analysis of inter-integrated circuit router
GB2410578B (en) * 2004-02-02 2008-04-16 Surfkitchen Inc Routing system
JP2006164185A (en) * 2004-12-10 2006-06-22 Matsushita Electric Ind Co Ltd Debug device
CN101124547A (en) * 2004-12-20 2008-02-13 皇家飞利浦电子股份有限公司 A testable multiprocessor system and a method for testing a processor system
JP5245617B2 (en) * 2008-07-30 2013-07-24 富士通株式会社 Register control circuit and register control method
US8145749B2 (en) * 2008-08-11 2012-03-27 International Business Machines Corporation Data processing in a hybrid computing environment
US8230442B2 (en) 2008-09-05 2012-07-24 International Business Machines Corporation Executing an accelerator application program in a hybrid computing environment
US8843880B2 (en) * 2009-01-27 2014-09-23 International Business Machines Corporation Software development for a hybrid computing environment
US8255909B2 (en) 2009-01-28 2012-08-28 International Business Machines Corporation Synchronizing access to resources in a hybrid computing environment
US9170864B2 (en) 2009-01-29 2015-10-27 International Business Machines Corporation Data processing in a hybrid computing environment
US9417905B2 (en) 2010-02-03 2016-08-16 International Business Machines Corporation Terminating an accelerator application program in a hybrid computing environment
US9015443B2 (en) 2010-04-30 2015-04-21 International Business Machines Corporation Reducing remote reads of memory in a hybrid computing environment

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US4495598A (en) * 1982-09-29 1985-01-22 Mcdonnell Douglas Corporation Computer rotate function
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
USH570H (en) * 1986-06-03 1989-01-03 The United States Of America As Represented By The Secretary Of The Navy Fast Fourier transform data address pre-scrambler circuit
US4896133A (en) * 1987-02-10 1990-01-23 Davin Computer Corporation Parallel string processor and method for a minicomputer
US5073864A (en) * 1987-02-10 1991-12-17 Davin Computer Corporation Parallel string processor and method for a minicomputer
US5428811A (en) * 1990-12-20 1995-06-27 Intel Corporation Interface between a register file which arbitrates between a number of single cycle and multiple cycle functional units
EP0550290A2 (en) * 1992-01-02 1993-07-07 Amdahl Corporation CPU register array
GB9226463D0 (en) * 1992-12-18 1993-02-10 Univ London Integrated circuits
EP1229440B1 (en) * 1993-05-27 2007-05-02 Matsushita Electric Industrial Co., Ltd. Program converting unit and processor improved in address management
US5640399A (en) * 1993-10-20 1997-06-17 Lsi Logic Corporation Single chip network router
US5809036A (en) * 1993-11-29 1998-09-15 Motorola, Inc. Boundary-scan testable system and method
JP3739797B2 (en) * 1995-10-06 2006-01-25 パトリオット サイエンティフィック コーポレイション Reduced instruction set computer microprocessor structure
US6088783A (en) * 1996-02-16 2000-07-11 Morton; Steven G DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5960209A (en) * 1996-03-11 1999-09-28 Mitel Corporation Scaleable digital signal processor with parallel architecture
US5864738A (en) * 1996-03-13 1999-01-26 Cray Research, Inc. Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
JP2869379B2 (en) * 1996-03-15 1999-03-10 三菱電機株式会社 Processor synthesis system and processor synthesis method
DE69837299T2 (en) * 1997-01-22 2007-06-28 Matsushita Electric Industrial Co., Ltd., Kadoma System and method for fast Fourier transformation
US6385647B1 (en) * 1997-08-18 2002-05-07 Mci Communications Corporations System for selectively routing data via either a network that supports Internet protocol or via satellite transmission network based on size of the data
US6029241A (en) * 1997-10-28 2000-02-22 Microchip Technology Incorporated Processor architecture scheme having multiple bank address override sources for supplying address values and method therefor
US6351758B1 (en) * 1998-02-13 2002-02-26 Texas Instruments Incorporated Bit and digit reversal methods
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Also Published As

Publication number Publication date
AU2001222161A1 (en) 2002-02-13
WO2002010994A1 (en) 2002-02-07
WO2002010947A3 (en) 2002-10-17
US20020013796A1 (en) 2002-01-31
WO2002010947A2 (en) 2002-02-07
US20020029289A1 (en) 2002-03-07

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