AU2001241906A1 - Method and apparatus for critical and false path verification - Google Patents

Method and apparatus for critical and false path verification

Info

Publication number
AU2001241906A1
AU2001241906A1 AU2001241906A AU4190601A AU2001241906A1 AU 2001241906 A1 AU2001241906 A1 AU 2001241906A1 AU 2001241906 A AU2001241906 A AU 2001241906A AU 4190601 A AU4190601 A AU 4190601A AU 2001241906 A1 AU2001241906 A1 AU 2001241906A1
Authority
AU
Australia
Prior art keywords
critical
path verification
false path
false
verification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001241906A
Other languages
English (en)
Inventor
Han-Hsun Chao
Rahul Razdan
Alexander Saldanha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2001241906A1 publication Critical patent/AU2001241906A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AU2001241906A 2000-03-02 2001-03-01 Method and apparatus for critical and false path verification Abandoned AU2001241906A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09517654 2000-03-02
US09/517,654 US6714902B1 (en) 2000-03-02 2000-03-02 Method and apparatus for critical and false path verification
PCT/US2001/006623 WO2001065759A2 (en) 2000-03-02 2001-03-01 Method and apparatus for critical and false path verification

Publications (1)

Publication Number Publication Date
AU2001241906A1 true AU2001241906A1 (en) 2001-09-12

Family

ID=24060671

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001241906A Abandoned AU2001241906A1 (en) 2000-03-02 2001-03-01 Method and apparatus for critical and false path verification

Country Status (5)

Country Link
US (1) US6714902B1 (de)
EP (3) EP1266312A4 (de)
JP (1) JP2003526149A (de)
AU (1) AU2001241906A1 (de)
WO (1) WO2001065759A2 (de)

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US6684375B2 (en) * 2000-11-22 2004-01-27 Matsushita Electric Industrial Co., Ltd. Delay distribution calculation method, circuit evaluation method and false path extraction method
US7117458B1 (en) * 2002-04-30 2006-10-03 Unisys Corporation Identifying specific netlist gates for use in code coverage testing
US7587690B1 (en) * 2003-04-29 2009-09-08 Cadence Design Systems, Inc. Method and system for global coverage analysis
JP4128131B2 (ja) * 2003-11-19 2008-07-30 富士通株式会社 フォールスパス検出プログラム
US7260799B2 (en) * 2005-02-10 2007-08-21 International Business Machines Corporation Exploiting suspected redundancy for enhanced design verification
US7458046B2 (en) * 2005-07-19 2008-11-25 Fujitsu Limited Estimating the difficulty level of a formal verification problem
JP2007102631A (ja) * 2005-10-06 2007-04-19 Matsushita Electric Ind Co Ltd 論理回路設計支援装置およびこれを用いた論理回路設計支援方法
JP4682059B2 (ja) * 2006-03-02 2011-05-11 富士通株式会社 フォールスパス記述情報生成プログラム、フォールスパス記述情報生成装置およびフォールスパス記述情報生成方法
US7650581B2 (en) * 2007-05-15 2010-01-19 Atrenta, Inc. Method for modeling and verifying timing exceptions
US7716615B2 (en) * 2007-08-31 2010-05-11 International Business Machines Corporation Redundant critical path circuits to meet performance requirement
US7739637B2 (en) * 2007-08-31 2010-06-15 International Business Machines Corporation Partial good schema for integrated circuits having parallel execution units
US7913208B2 (en) * 2007-10-11 2011-03-22 International Business Machines Corporation Optimal simplification of constraint-based testbenches
US7882473B2 (en) * 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification
US8001072B2 (en) * 2008-06-19 2011-08-16 Microsoft Corporation Determining satisfiability of a function with arbitrary domain constraints
US20100088678A1 (en) * 2008-10-08 2010-04-08 Alturki Musab Method and apparatus for the formal specification and analysis of timing properties in software systems
US20100250187A1 (en) * 2009-03-25 2010-09-30 Imec Method and system for analyzing performance metrics of array type circuits under process variability
US8413085B2 (en) * 2011-04-09 2013-04-02 Chipworks Inc. Digital netlist partitioning system for faster circuit reverse-engineering
US8495537B1 (en) * 2012-01-12 2013-07-23 International Business Machines Corporation Timing analysis of an array circuit cross section
US8671375B1 (en) * 2012-11-09 2014-03-11 National Taiwan University Functional timing analysis method for circuit timing verification
US8978001B1 (en) 2013-09-11 2015-03-10 International Business Machines Corporation Enhanced case-splitting based property checking
US9081927B2 (en) 2013-10-04 2015-07-14 Jasper Design Automation, Inc. Manipulation of traces for debugging a circuit design
US9983977B2 (en) 2014-02-26 2018-05-29 Western Michigan University Research Foundation Apparatus and method for testing computer program implementation against a design model
US9965575B2 (en) * 2015-09-18 2018-05-08 Real Intent, Inc. Methods and systems for correcting X-pessimism in gate-level simulation or emulation
US10275561B2 (en) * 2016-05-27 2019-04-30 Taiwan Semiconductor Manufacturing Company Limited Method for eliminating false paths of a circuit unit to be implemented using a system
US10049174B2 (en) * 2016-12-16 2018-08-14 Synopsys, Inc. Exact delay synthesis
US10325051B2 (en) * 2016-12-16 2019-06-18 Synopsys, Inc. Exact delay synthesis
US10331826B2 (en) 2017-04-20 2019-06-25 Texas Instruments Incorporated False path timing exception handler circuit
CN108763660B (zh) * 2018-05-08 2022-05-03 中国人民解放军国防科技大学 组合电路瞬态脉冲重汇聚现象可满足性分析方法及系统
CN111427798A (zh) * 2020-04-14 2020-07-17 北京计算机技术及应用研究所 一种ip核超长路径可组合证明方法

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US4527249A (en) 1982-10-22 1985-07-02 Control Data Corporation Simulator system for logic design validation
US4722071A (en) * 1985-04-19 1988-01-26 Pertron Controls, Corporation Compiler for evaluating Boolean expressions
US4924430A (en) 1988-01-28 1990-05-08 Teradyne, Inc. Static timing analysis of semiconductor digital circuits
US5095454A (en) 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
US5191541A (en) 1990-05-14 1993-03-02 Sun Microsystems, Inc. Method and apparatus to improve static path analysis of digital circuits
US5648909A (en) * 1992-06-12 1997-07-15 Digital Equipment Corporation Static timing verification in the presence of logically false paths
US5355321A (en) 1992-06-12 1994-10-11 Digital Equipment Corporation Static timing verification
US5448497A (en) * 1992-09-08 1995-09-05 Nec Research Institute, Inc. Exploiting multi-cycle false paths in the performance optimization of sequential circuits
US5657239A (en) * 1992-10-30 1997-08-12 Digital Equipment Corporation Timing verification using synchronizers and timing constraints
US5600787A (en) * 1994-05-31 1997-02-04 Motorola, Inc. Method and data processing system for verifying circuit test vectors
US5805459A (en) * 1995-04-24 1998-09-08 Texas Instruments Incorporated Method of measuring activity in a digital circuit
US5896300A (en) * 1996-08-30 1999-04-20 Avant| Corporation Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets
US5946475A (en) * 1997-01-21 1999-08-31 International Business Machines Corporation Method for performing transistor-level static timing analysis of a logic circuit
US6086626A (en) * 1997-05-16 2000-07-11 Fijutsu Limited Method for verification of combinational circuits using a filtering oriented approach
US6097884A (en) * 1997-12-08 2000-08-01 Lsi Logic Corporation Probe points and markers for critical paths and integrated circuits
US6026222A (en) 1997-12-23 2000-02-15 Nec Usa, Inc. System for combinational equivalence checking

Also Published As

Publication number Publication date
EP1843267A1 (de) 2007-10-10
EP1845463A1 (de) 2007-10-17
JP2003526149A (ja) 2003-09-02
EP1266312A4 (de) 2004-12-29
WO2001065759A2 (en) 2001-09-07
EP1266312A2 (de) 2002-12-18
US6714902B1 (en) 2004-03-30
WO2001065759A3 (en) 2002-02-21

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