AU1824399A - Flicker filter and interlacer implemented in a television system displaying network application data - Google Patents

Flicker filter and interlacer implemented in a television system displaying network application data

Info

Publication number
AU1824399A
AU1824399A AU18243/99A AU1824399A AU1824399A AU 1824399 A AU1824399 A AU 1824399A AU 18243/99 A AU18243/99 A AU 18243/99A AU 1824399 A AU1824399 A AU 1824399A AU 1824399 A AU1824399 A AU 1824399A
Authority
AU
Australia
Prior art keywords
interlacer
implemented
application data
network application
television system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU18243/99A
Other languages
English (en)
Inventor
Vlad Bril
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TeleCruz Tech Inc
Original Assignee
TeleCruz Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TeleCruz Tech Inc filed Critical TeleCruz Tech Inc
Publication of AU1824399A publication Critical patent/AU1824399A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
    • H04N7/012—Conversion between an interlaced and a progressive signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
    • H04N7/0132—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S348/00—Television
    • Y10S348/91—Flicker reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Television Systems (AREA)
  • Picture Signal Circuits (AREA)
AU18243/99A 1997-12-31 1998-12-14 Flicker filter and interlacer implemented in a television system displaying network application data Abandoned AU1824399A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09001304 1997-12-31
US09/001,304 US6072530A (en) 1997-12-31 1997-12-31 Flicker filter and interlacer implemented in a television system displaying network application data
PCT/US1998/026545 WO1999034596A1 (en) 1997-12-31 1998-12-14 Flicker filter and interlacer implemented in a television system displaying network application data

Publications (1)

Publication Number Publication Date
AU1824399A true AU1824399A (en) 1999-07-19

Family

ID=21695353

Family Applications (1)

Application Number Title Priority Date Filing Date
AU18243/99A Abandoned AU1824399A (en) 1997-12-31 1998-12-14 Flicker filter and interlacer implemented in a television system displaying network application data

Country Status (8)

Country Link
US (1) US6072530A (enExample)
EP (1) EP1044562A1 (enExample)
JP (1) JP2002500479A (enExample)
KR (1) KR20010032565A (enExample)
CN (1) CN1283363A (enExample)
AU (1) AU1824399A (enExample)
CA (1) CA2316234C (enExample)
WO (1) WO1999034596A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4008580B2 (ja) * 1998-06-25 2007-11-14 株式会社東芝 表示制御装置およびインターレースデータ表示制御方法
FR2797979B1 (fr) * 1999-08-24 2002-05-24 St Microelectronics Sa Procede et systeme de filtrage anti-scintillement
US7034887B2 (en) * 2002-07-15 2006-04-25 Seiko Epson Corporation Method and apparatus for flicker filtering interlaced display data
EP1511004A3 (en) 2003-08-19 2010-01-27 Sony Corporation Memory controller, memory control method, rate conversion apparatus, rate conversion method, image-signal-processing apparatus, image-signal-processing method, and program for executing these methods
JP4661036B2 (ja) * 2003-08-19 2011-03-30 ソニー株式会社 メモリコントローラおよびメモリコントロール方法、その方法を実行するためのプログラム
CN102148920B (zh) * 2010-02-09 2013-03-13 联发科技股份有限公司 同步信号限幅装置与同步信号限幅方法
KR101995553B1 (ko) * 2013-01-16 2019-07-03 삼성디스플레이 주식회사 표시 장치의 타이밍 컨트롤러 및 이의 구동 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327156A (en) * 1990-11-09 1994-07-05 Fuji Photo Film Co., Ltd. Apparatus for processing signals representative of a computer graphics image and a real image including storing processed signals back into internal memory
US5355328A (en) * 1991-09-27 1994-10-11 Northshore Laboratories, Inc. Resampling apparatus suitable for resizing a video image
US5510843A (en) * 1994-09-30 1996-04-23 Cirrus Logic, Inc. Flicker reduction and size adjustment for video controller with interlaced video output
US5742349A (en) * 1996-05-07 1998-04-21 Chrontel, Inc. Memory efficient video graphics subsystem with vertical filtering and scan rate conversion
US5781241A (en) * 1996-11-08 1998-07-14 Chrontel, Inc. Apparatus and method to convert computer graphics signals to television video signals with vertical and horizontal scaling requiring no frame buffers

Also Published As

Publication number Publication date
CN1283363A (zh) 2001-02-07
CA2316234A1 (en) 1999-07-08
WO1999034596A1 (en) 1999-07-08
KR20010032565A (ko) 2001-04-25
JP2002500479A (ja) 2002-01-08
CA2316234C (en) 2008-03-04
EP1044562A1 (en) 2000-10-18
US6072530A (en) 2000-06-06

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase