AU1757797A - Digit line architecture for dynamic memory - Google Patents

Digit line architecture for dynamic memory

Info

Publication number
AU1757797A
AU1757797A AU17577/97A AU1757797A AU1757797A AU 1757797 A AU1757797 A AU 1757797A AU 17577/97 A AU17577/97 A AU 17577/97A AU 1757797 A AU1757797 A AU 1757797A AU 1757797 A AU1757797 A AU 1757797A
Authority
AU
Australia
Prior art keywords
dynamic memory
digit line
line architecture
architecture
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU17577/97A
Inventor
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/701,749 external-priority patent/US6043562A/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of AU1757797A publication Critical patent/AU1757797A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
AU17577/97A 1996-02-01 1997-01-29 Digit line architecture for dynamic memory Abandoned AU1757797A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US1029396P 1996-02-01 1996-02-01
US010293 1996-02-01
US08/701,749 US6043562A (en) 1996-01-26 1996-08-22 Digit line architecture for dynamic memory
US701749 1996-08-22
PCT/US1997/001569 WO1997028532A1 (en) 1996-02-01 1997-01-29 Digit line architecture for dynamic memory

Publications (1)

Publication Number Publication Date
AU1757797A true AU1757797A (en) 1997-08-22

Family

ID=26681001

Family Applications (1)

Application Number Title Priority Date Filing Date
AU17577/97A Abandoned AU1757797A (en) 1996-02-01 1997-01-29 Digit line architecture for dynamic memory

Country Status (2)

Country Link
AU (1) AU1757797A (en)
WO (1) WO1997028532A1 (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864496A (en) * 1997-09-29 1999-01-26 Siemens Aktiengesellschaft High density semiconductor memory having diagonal bit lines and dual word lines
US6069815A (en) * 1997-12-18 2000-05-30 Siemens Aktiengesellschaft Semiconductor memory having hierarchical bit line and/or word line architecture
JP2001084768A (en) * 1999-09-10 2001-03-30 Mitsubishi Electric Corp Semiconductor device
US6327170B1 (en) * 1999-09-28 2001-12-04 Infineon Technologies Ag Reducing impact of coupling noise in multi-level bitline architecture
DE10026654A1 (en) * 2000-05-29 2001-12-13 Infineon Technologies Ag Digital memory circuit
US6549476B2 (en) * 2001-04-09 2003-04-15 Micron Technology, Inc. Device and method for using complementary bits in a memory array
US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
US7742324B2 (en) 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
US9190494B2 (en) 2008-02-19 2015-11-17 Micron Technology, Inc. Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin
US7915659B2 (en) 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
US7808042B2 (en) 2008-03-20 2010-10-05 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US7898857B2 (en) 2008-03-20 2011-03-01 Micron Technology, Inc. Memory structure having volatile and non-volatile memory portions
US8546876B2 (en) 2008-03-20 2013-10-01 Micron Technology, Inc. Systems and devices including multi-transistor cells and methods of using, making, and operating the same
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
US8076229B2 (en) 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
US8148776B2 (en) 2008-09-15 2012-04-03 Micron Technology, Inc. Transistor with a passive gate
US8294511B2 (en) 2010-11-19 2012-10-23 Micron Technology, Inc. Vertically stacked fin transistors and methods of fabricating and operating the same
US11393845B2 (en) * 2020-08-28 2022-07-19 Micron Technology, Inc. Microelectronic devices, and related memory devices and electronic systems

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3173745D1 (en) * 1981-10-30 1986-03-20 Ibm Deutschland Fet memory
JPS63183691A (en) * 1987-01-26 1988-07-29 Mitsubishi Electric Corp Semiconductor storage device
US5014110A (en) * 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
US5107459A (en) * 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array
KR100215595B1 (en) * 1993-09-21 1999-08-16 니시무로 타이죠 Dynamic semiconductor memory device

Also Published As

Publication number Publication date
WO1997028532A1 (en) 1997-08-07

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