AU1583001A - Method and system for wafer and device-level testing of an integrated circuit - Google Patents

Method and system for wafer and device-level testing of an integrated circuit

Info

Publication number
AU1583001A
AU1583001A AU15830/01A AU1583001A AU1583001A AU 1583001 A AU1583001 A AU 1583001A AU 15830/01 A AU15830/01 A AU 15830/01A AU 1583001 A AU1583001 A AU 1583001A AU 1583001 A AU1583001 A AU 1583001A
Authority
AU
Australia
Prior art keywords
wafer
integrated circuit
level testing
testing
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU15830/01A
Inventor
Don Mccord
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU1583001A publication Critical patent/AU1583001A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
AU15830/01A 1999-11-05 2000-11-03 Method and system for wafer and device-level testing of an integrated circuit Abandoned AU1583001A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16391499P 1999-11-05 1999-11-05
US60163914 1999-11-05
PCT/US2000/030372 WO2001035110A1 (en) 1999-11-05 2000-11-03 Method and system for wafer and device-level testing of an integrated circuit

Publications (1)

Publication Number Publication Date
AU1583001A true AU1583001A (en) 2001-06-06

Family

ID=22592149

Family Applications (1)

Application Number Title Priority Date Filing Date
AU15830/01A Abandoned AU1583001A (en) 1999-11-05 2000-11-03 Method and system for wafer and device-level testing of an integrated circuit

Country Status (2)

Country Link
AU (1) AU1583001A (en)
WO (1) WO2001035110A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001063311A2 (en) * 2000-02-22 2001-08-30 Don Mccord Method and system for wafer and device-level testing of an integrated circuit
AU2001296891A1 (en) * 2000-09-22 2002-04-02 Don Mccord Method and system for wafer and device-level testing of an integrated circuit
CN110763969A (en) * 2019-08-08 2020-02-07 浙江大学 Light emitting diode and solar cell aging test system
CN112098810A (en) * 2020-09-27 2020-12-18 国网冀北电力有限公司计量中心 Chip testing device, system and method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268639A (en) * 1992-06-05 1993-12-07 Rambus, Inc. Testing timing parameters of high speed integrated circuit devices

Also Published As

Publication number Publication date
WO2001035110A1 (en) 2001-05-17

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase