AU1345197A - Microarchitecture for indicating that the packed data state is full or empty - Google Patents

Microarchitecture for indicating that the packed data state is full or empty

Info

Publication number
AU1345197A
AU1345197A AU13451/97A AU1345197A AU1345197A AU 1345197 A AU1345197 A AU 1345197A AU 13451/97 A AU13451/97 A AU 13451/97A AU 1345197 A AU1345197 A AU 1345197A AU 1345197 A AU1345197 A AU 1345197A
Authority
AU
Australia
Prior art keywords
floating point
packed data
instruction
tags
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU13451/97A
Other languages
English (en)
Inventor
David Bistry
Carole Dulong
Benny Eitan
Eiichi Kowashi
Larry M Mennemeier
Millind Mittal
Alexander D. Peleg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU1345197A publication Critical patent/AU1345197A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • General Preparation And Processing Of Foods (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AU13451/97A 1995-12-19 1996-12-17 Microarchitecture for indicating that the packed data state is full or empty Abandoned AU1345197A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US575686 1995-12-19
US08/575,686 US5857096A (en) 1995-12-19 1995-12-19 Microarchitecture for implementing an instruction to clear the tags of a stack reference register file
PCT/US1996/020516 WO1997022920A1 (en) 1995-12-19 1996-12-17 Microarchitecture for indicating that the packed data state is full or empty

Publications (1)

Publication Number Publication Date
AU1345197A true AU1345197A (en) 1997-07-14

Family

ID=24301308

Family Applications (1)

Application Number Title Priority Date Filing Date
AU13451/97A Abandoned AU1345197A (en) 1995-12-19 1996-12-17 Microarchitecture for indicating that the packed data state is full or empty

Country Status (4)

Country Link
US (1) US5857096A (enExample)
AU (1) AU1345197A (enExample)
TW (1) TW320708B (enExample)
WO (1) WO1997022920A1 (enExample)

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CN100412786C (zh) 1994-12-02 2008-08-20 英特尔公司 可以对复合操作数进行压缩操作的微处理器
US5940859A (en) * 1995-12-19 1999-08-17 Intel Corporation Emptying packed data state during execution of packed data instructions
US6792523B1 (en) * 1995-12-19 2004-09-14 Intel Corporation Processor with instructions that operate on different data types stored in the same single logical register file
US5701508A (en) 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
US6088786A (en) * 1997-06-27 2000-07-11 Sun Microsystems, Inc. Method and system for coupling a stack based processor to register based functional unit
US6405234B2 (en) * 1997-09-11 2002-06-11 International Business Machines Corporation Full time operating system
US6065114A (en) * 1998-04-21 2000-05-16 Idea Corporation Cover instruction and asynchronous backing store switch
US6247113B1 (en) * 1998-05-27 2001-06-12 Arm Limited Coprocessor opcode division by data type
US6212624B1 (en) * 1998-09-30 2001-04-03 Intel Corporation Selective canonizing on mode transitions
US7882325B2 (en) * 2007-12-21 2011-02-01 Intel Corporation Method and apparatus for a double width load using a single width load port
JP2010122787A (ja) * 2008-11-18 2010-06-03 Panasonic Corp 半導体集積回路及びレジスタアドレス制御装置

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US3723715A (en) * 1971-08-25 1973-03-27 Ibm Fast modulo threshold operator binary adder for multi-number additions
US4161784A (en) * 1978-01-05 1979-07-17 Honeywell Information Systems, Inc. Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
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JPS6297060A (ja) * 1985-10-23 1987-05-06 Mitsubishi Electric Corp デイジタルシグナルプロセツサ
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US4989168A (en) * 1987-11-30 1991-01-29 Fujitsu Limited Multiplying unit in a computer system, capable of population counting
US5008812A (en) * 1988-03-18 1991-04-16 Digital Equipment Corporation Context switching method and apparatus for use in a vector processing system
US5241635A (en) * 1988-11-18 1993-08-31 Massachusetts Institute Of Technology Tagged token data processing system with operand matching in activation frames
KR920007505B1 (ko) * 1989-02-02 1992-09-04 정호선 신경회로망을 이용한 곱셈기
US5127098A (en) * 1989-04-12 1992-06-30 Sun Microsystems, Inc. Method and apparatus for the context switching of devices
JPH03139726A (ja) * 1989-10-26 1991-06-13 Hitachi Ltd 命令読出し制御方式
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US5522051A (en) * 1992-07-29 1996-05-28 Intel Corporation Method and apparatus for stack manipulation in a pipelined processor
US5367650A (en) * 1992-07-31 1994-11-22 Intel Corporation Method and apparauts for parallel exchange operation in a pipelined processor
US5519841A (en) * 1992-11-12 1996-05-21 Digital Equipment Corporation Multi instruction register mapper
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US5499352A (en) * 1993-09-30 1996-03-12 Intel Corporation Floating point register alias table FXCH and retirement floating point register array
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US5546554A (en) * 1994-02-02 1996-08-13 Sun Microsystems, Inc. Apparatus for dynamic register management in a floating point unit
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Also Published As

Publication number Publication date
WO1997022920A1 (en) 1997-06-26
US5857096A (en) 1999-01-05
TW320708B (enExample) 1997-11-21

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Legal Events

Date Code Title Description
MK5 Application lapsed section 142(2)(e) - patent request and compl. specification not accepted