ATE516533T1 - System mit mehreren prozessoren und verfahren zu seinem betrieb - Google Patents

System mit mehreren prozessoren und verfahren zu seinem betrieb

Info

Publication number
ATE516533T1
ATE516533T1 AT08767909T AT08767909T ATE516533T1 AT E516533 T1 ATE516533 T1 AT E516533T1 AT 08767909 T AT08767909 T AT 08767909T AT 08767909 T AT08767909 T AT 08767909T AT E516533 T1 ATE516533 T1 AT E516533T1
Authority
AT
Austria
Prior art keywords
state
variables
interrupt
processor
buffer memory
Prior art date
Application number
AT08767909T
Other languages
English (en)
Inventor
Uwe Kranich
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE516533T1 publication Critical patent/ATE516533T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Electrotherapy Devices (AREA)
  • Control Of Eletrric Generators (AREA)
AT08767909T 2007-05-31 2008-05-28 System mit mehreren prozessoren und verfahren zu seinem betrieb ATE516533T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102007025397A DE102007025397B4 (de) 2007-05-31 2007-05-31 System mit mehreren Prozessoren und Verfahren zu seinem Betrieb
US12/014,868 US7689809B2 (en) 2007-05-31 2008-01-16 Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system
PCT/US2008/006744 WO2008153797A1 (en) 2007-05-31 2008-05-28 System comprising a plurality of processors and methods of operating the same

Publications (1)

Publication Number Publication Date
ATE516533T1 true ATE516533T1 (de) 2011-07-15

Family

ID=39917349

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08767909T ATE516533T1 (de) 2007-05-31 2008-05-28 System mit mehreren prozessoren und verfahren zu seinem betrieb

Country Status (10)

Country Link
US (1) US7689809B2 (de)
EP (1) EP2171575B1 (de)
JP (1) JP5295228B2 (de)
KR (1) KR101485068B1 (de)
CN (1) CN101730881B (de)
AT (1) ATE516533T1 (de)
DE (1) DE102007025397B4 (de)
GB (1) GB2461841A (de)
TW (1) TWI467490B (de)
WO (1) WO2008153797A1 (de)

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US20100138575A1 (en) 2008-12-01 2010-06-03 Micron Technology, Inc. Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices
US7930519B2 (en) * 2008-12-17 2011-04-19 Advanced Micro Devices, Inc. Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
JP4572259B1 (ja) * 2009-04-27 2010-11-04 株式会社フォティーンフォティ技術研究所 情報機器、プログラム及び不正なプログラムコードの実行防止方法
CN101882098B (zh) * 2009-07-10 2012-07-11 威盛电子股份有限公司 微处理器集成电路以及相关除错方法
US9710275B2 (en) * 2012-11-05 2017-07-18 Nvidia Corporation System and method for allocating memory of differing properties to shared data objects
US20160147536A1 (en) * 2014-11-24 2016-05-26 International Business Machines Corporation Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes
US9747108B2 (en) * 2015-03-27 2017-08-29 Intel Corporation User-level fork and join processors, methods, systems, and instructions
US20170090927A1 (en) * 2015-09-30 2017-03-30 Paul Caprioli Control transfer instructions indicating intent to call or return
US10924416B2 (en) 2016-03-23 2021-02-16 Clavister Ab Method for traffic shaping using a serial packet processing algorithm and a parallel packet processing algorithm
EP3433985B1 (de) * 2016-03-23 2021-01-27 Clavister AB Verfahren zur verkehrsformung mittels eines seriellen paketverarbeitungsalgorithmus und paralleler paketverarbeitungsalgorithmus
US10541868B2 (en) * 2017-02-24 2020-01-21 Quanta Computer Inc. System and method for automatically updating bios setup options
US10831503B2 (en) 2018-11-06 2020-11-10 International Business Machines Corporation Saving and restoring machine state between multiple executions of an instruction
US10831502B2 (en) * 2018-11-06 2020-11-10 International Business Machines Corporation Migration of partially completed instructions
US10831478B2 (en) 2018-11-06 2020-11-10 International Business Machines Corporation Sort and merge instruction for a general-purpose processor
CN111181169B (zh) * 2020-01-13 2023-10-20 深圳市禾望电气股份有限公司 Svg并联运行系统的控制方法、装置以及存储介质
CN113094111B (zh) * 2021-04-16 2024-01-09 三星（中国）半导体有限公司 设备以及设备的启动方法

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US5197138A (en) * 1989-12-26 1993-03-23 Digital Equipment Corporation Reporting delayed coprocessor exceptions to code threads having caused the exceptions by saving and restoring exception state during code thread switching
US5481719A (en) * 1994-09-09 1996-01-02 International Business Machines Corporation Exception handling method and apparatus for a microkernel data processing system
US5812823A (en) * 1996-01-02 1998-09-22 International Business Machines Corporation Method and system for performing an emulation context save and restore that is transparent to the operating system
US6003129A (en) * 1996-08-19 1999-12-14 Samsung Electronics Company, Ltd. System and method for handling interrupt and exception events in an asymmetric multiprocessor architecture
US6058465A (en) * 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US6230259B1 (en) * 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6574725B1 (en) * 1999-11-01 2003-06-03 Advanced Micro Devices, Inc. Method and mechanism for speculatively executing threads of instructions
US6651163B1 (en) * 2000-03-08 2003-11-18 Advanced Micro Devices, Inc. Exception handling with reduced overhead in a multithreaded multiprocessing system
KR100456630B1 (ko) * 2001-12-11 2004-11-10 한국전자통신연구원 프로세서간 통신을 위한 인터럽트 중계 장치 및 방법
US7765388B2 (en) * 2003-09-17 2010-07-27 Broadcom Corporation Interrupt verification support mechanism
JP4457047B2 (ja) * 2005-06-22 2010-04-28 株式会社ルネサステクノロジ マルチプロセッサシステム
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US7912302B2 (en) * 2006-09-21 2011-03-22 Analog Devices, Inc. Multiprocessor decoder system and method

Also Published As

Publication number Publication date
US20080301408A1 (en) 2008-12-04
US7689809B2 (en) 2010-03-30
TW200905566A (en) 2009-02-01
EP2171575B1 (de) 2011-07-13
JP5295228B2 (ja) 2013-09-18
GB0920863D0 (en) 2010-01-13
KR101485068B1 (ko) 2015-01-21
TWI467490B (zh) 2015-01-01
EP2171575A1 (de) 2010-04-07
DE102007025397B4 (de) 2010-07-15
DE102007025397A1 (de) 2008-12-04
CN101730881A (zh) 2010-06-09
GB2461841A (en) 2010-01-20
KR20100036279A (ko) 2010-04-07
WO2008153797A1 (en) 2008-12-18
CN101730881B (zh) 2014-07-09
JP2010529533A (ja) 2010-08-26

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