ATE513263T1 - Qualifizierung von ereigniserkennung durch thread-id und thread-privilegstufe - Google Patents

Qualifizierung von ereigniserkennung durch thread-id und thread-privilegstufe

Info

Publication number
ATE513263T1
ATE513263T1 AT01273024T AT01273024T ATE513263T1 AT E513263 T1 ATE513263 T1 AT E513263T1 AT 01273024 T AT01273024 T AT 01273024T AT 01273024 T AT01273024 T AT 01273024T AT E513263 T1 ATE513263 T1 AT E513263T1
Authority
AT
Austria
Prior art keywords
thread
event
events
privilege level
processor
Prior art date
Application number
AT01273024T
Other languages
English (en)
Inventor
Michael Cranford
Scott Rodgers
Stavos Kalafatis
H M Sprunt
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE513263T1 publication Critical patent/ATE513263T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/348Circuit details, i.e. tracer hardware
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/86Event-based monitoring
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88Monitoring involving counting
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885Monitoring specific for caches

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)
  • Burglar Alarm Systems (AREA)
  • Supports For Plants (AREA)
AT01273024T 2000-12-29 2001-11-26 Qualifizierung von ereigniserkennung durch thread-id und thread-privilegstufe ATE513263T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/751,813 US7448025B2 (en) 2000-12-29 2000-12-29 Qualification of event detection by thread ID and thread privilege level
PCT/US2001/044083 WO2002054245A2 (en) 2000-12-29 2001-11-26 Qualification of event detection by thread id and thread privilege level

Publications (1)

Publication Number Publication Date
ATE513263T1 true ATE513263T1 (de) 2011-07-15

Family

ID=25023586

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01273024T ATE513263T1 (de) 2000-12-29 2001-11-26 Qualifizierung von ereigniserkennung durch thread-id und thread-privilegstufe

Country Status (10)

Country Link
US (1) US7448025B2 (de)
EP (1) EP1407361B1 (de)
KR (1) KR100528151B1 (de)
CN (1) CN100492313C (de)
AT (1) ATE513263T1 (de)
AU (1) AU2002217850A1 (de)
BR (1) BR0116654A (de)
RU (1) RU2268483C2 (de)
TW (1) TW548593B (de)
WO (1) WO2002054245A2 (de)

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6970809B2 (en) * 2001-08-29 2005-11-29 International Business Machines Corporation Automated configuration of on-circuit facilities
GB2389931B (en) * 2002-06-07 2005-12-14 Advanced Risc Mach Ltd Generation of trace elements within a data processing apparatus
GB2389432B (en) * 2002-06-07 2005-09-07 Advanced Risc Mach Ltd Instruction tracing in data processing systems
US7197671B2 (en) 2002-06-07 2007-03-27 Arm Limited Generation of trace elements within a data processing apparatus
GB2402504A (en) * 2002-11-12 2004-12-08 Advanced Risc Mach Ltd Processor performance calculation
US7194385B2 (en) * 2002-11-12 2007-03-20 Arm Limited Performance level setting of a data processing system
US7849465B2 (en) * 2003-02-19 2010-12-07 Intel Corporation Programmable event driven yield mechanism which may activate service threads
US7487502B2 (en) 2003-02-19 2009-02-03 Intel Corporation Programmable event driven yield mechanism which may activate other threads
CN100507859C (zh) * 2003-04-22 2009-07-01 英业达股份有限公司 串行端口多线程测试方法
US7937691B2 (en) * 2003-09-30 2011-05-03 International Business Machines Corporation Method and apparatus for counting execution of specific instructions and accesses to specific data locations
US20050071608A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for selectively counting instructions and data accesses
US20050071816A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically count instruction execution for applications
US20050071609A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically take an exception on specified instructions
US7395527B2 (en) 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US7373637B2 (en) 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
US7225309B2 (en) * 2003-10-09 2007-05-29 International Business Machines Corporation Method and system for autonomic performance improvements in an application via memory relocation
US7421681B2 (en) 2003-10-09 2008-09-02 International Business Machines Corporation Method and system for autonomic monitoring of semaphore operation in an application
US8381037B2 (en) 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US20050086455A1 (en) * 2003-10-16 2005-04-21 International Business Machines Corporation Method and apparatus for generating interrupts for specific types of instructions
US7458078B2 (en) * 2003-11-06 2008-11-25 International Business Machines Corporation Apparatus and method for autonomic hardware assisted thread stack tracking
US7257657B2 (en) * 2003-11-06 2007-08-14 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses for specific types of instructions
US7093081B2 (en) 2004-01-14 2006-08-15 International Business Machines Corporation Method and apparatus for identifying false cache line sharing
US7082486B2 (en) * 2004-01-14 2006-07-25 International Business Machines Corporation Method and apparatus for counting interrupts by type
US7114036B2 (en) * 2004-01-14 2006-09-26 International Business Machines Corporation Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected
US7197586B2 (en) * 2004-01-14 2007-03-27 International Business Machines Corporation Method and system for recording events of an interrupt using pre-interrupt handler and post-interrupt handler
US7392370B2 (en) 2004-01-14 2008-06-24 International Business Machines Corporation Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics
US7526757B2 (en) * 2004-01-14 2009-04-28 International Business Machines Corporation Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program
US7895382B2 (en) * 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7415705B2 (en) * 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US7496908B2 (en) * 2004-01-14 2009-02-24 International Business Machines Corporation Method and apparatus for optimizing code execution using annotated trace information having performance indicator and counter information
US7293164B2 (en) * 2004-01-14 2007-11-06 International Business Machines Corporation Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
US7290255B2 (en) * 2004-01-14 2007-10-30 International Business Machines Corporation Autonomic method and apparatus for local program code reorganization using branch count per instruction hardware
US7181599B2 (en) 2004-01-14 2007-02-20 International Business Machines Corporation Method and apparatus for autonomic detection of cache “chase tail” conditions and storage of instructions/data in “chase tail” data structure
US20050183065A1 (en) * 2004-02-13 2005-08-18 Wolczko Mario I. Performance counters in a multi-threaded processor
US8826241B2 (en) * 2004-02-16 2014-09-02 Oracle America, Inc. Instruction sampling in a multi-threaded processor
US20050188186A1 (en) * 2004-02-23 2005-08-25 Wolczko Mario I. Obtaining execution path information in an instruction sampling system
US7987453B2 (en) * 2004-03-18 2011-07-26 International Business Machines Corporation Method and apparatus for determining computer program flows autonomically using hardware assisted thread stack tracking and cataloged symbolic data
US8135915B2 (en) 2004-03-22 2012-03-13 International Business Machines Corporation Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator
US7526616B2 (en) 2004-03-22 2009-04-28 International Business Machines Corporation Method and apparatus for prefetching data from a data structure
US7299319B2 (en) 2004-03-22 2007-11-20 International Business Machines Corporation Method and apparatus for providing hardware assistance for code coverage
US7296130B2 (en) 2004-03-22 2007-11-13 International Business Machines Corporation Method and apparatus for providing hardware assistance for data access coverage on dynamically allocated data
US7421684B2 (en) * 2004-03-22 2008-09-02 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for data coverage
US7480899B2 (en) * 2004-03-22 2009-01-20 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for code coverage
US7249288B2 (en) * 2004-09-14 2007-07-24 Freescale Semiconductor, Inc. Method and apparatus for non-intrusive tracing
GB0420442D0 (en) * 2004-09-14 2004-10-20 Ignios Ltd Debug in a multicore architecture
US7797728B2 (en) * 2004-10-27 2010-09-14 Intel Corporation Mechanism to generate restricted and unrestricted execution environments
US20060129999A1 (en) * 2004-11-16 2006-06-15 Sony Computer Entertainment Inc. Methods and apparatus for using bookmarks in a trace buffer
US7200522B2 (en) * 2005-01-27 2007-04-03 International Business Machines Corporation Method, apparatus, and computer program product in a performance monitor for sampling all performance events generated by a processor
DE102005021986A1 (de) * 2005-05-09 2006-11-16 Robert Bosch Gmbh Verfahren zur Steuergeräte-Überwachung
US7490269B2 (en) * 2005-08-24 2009-02-10 Microsoft Corporation Noise accommodation in hardware and software testing
US7809928B1 (en) 2005-11-29 2010-10-05 Nvidia Corporation Generating event signals for performance register control using non-operative instructions
US8253748B1 (en) * 2005-11-29 2012-08-28 Nvidia Corporation Shader performance registers
JP4971679B2 (ja) * 2006-05-10 2012-07-11 ルネサスエレクトロニクス株式会社 プロセッサシステム及びプロセッサシステムの性能測定方法
US8214574B2 (en) * 2006-09-08 2012-07-03 Intel Corporation Event handling for architectural events at high privilege levels
US7768518B2 (en) * 2006-09-27 2010-08-03 Intel Corporation Enabling multiple instruction stream/multiple data stream extensions on microprocessors
US8171270B2 (en) * 2006-12-29 2012-05-01 Intel Corporation Asynchronous control transfer
US20090019797A1 (en) * 2007-07-19 2009-01-22 Cameron Todd Gunn Simplified Protective Cover Assembly
US8656411B2 (en) 2008-03-05 2014-02-18 Intel Corporation Technique for monitoring activity within an integrated circuit
JP2009301500A (ja) * 2008-06-17 2009-12-24 Nec Electronics Corp タスク処理システム及びタスク処理方法
TW201042467A (en) * 2009-05-26 2010-12-01 Toproot Technology Corp Ltd Enhanced pulse peripheral processor
US8650335B2 (en) * 2010-06-23 2014-02-11 International Business Machines Corporation Measurement facility for adapter functions
WO2013095570A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Instruction that specifies an application thread performance state
WO2013147887A1 (en) 2012-03-30 2013-10-03 Intel Corporation Context switching mechanism for a processing core having a general purpose cpu core and a tightly coupled accelerator
US9043654B2 (en) * 2012-12-07 2015-05-26 International Business Machines Corporation Avoiding processing flaws in a computer processor triggered by a predetermined sequence of hardware events
US20150052400A1 (en) 2013-08-19 2015-02-19 Concurix Corporation Breakpoint Setting Through a Debugger User Interface
US9021444B2 (en) * 2013-08-19 2015-04-28 Concurix Corporation Combined performance tracer and snapshot debugging system
US9465721B2 (en) 2013-08-19 2016-10-11 Microsoft Technology Licensing, Llc Snapshotting executing code with a modifiable snapshot definition
EP3080702B1 (de) * 2013-12-12 2019-08-14 Intel Corporation Verfahren zur erkennung von race-bedingungen
CN105487958B (zh) * 2015-11-24 2018-04-10 无锡江南计算技术研究所 处理器内部行为监测方法
US10042737B2 (en) 2016-08-31 2018-08-07 Microsoft Technology Licensing, Llc Program tracing for time travel debugging and analysis
US10031833B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10031834B2 (en) * 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10310963B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using index bits in a processor cache
US10324851B2 (en) 2016-10-20 2019-06-18 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using way-locking in a set-associative processor cache
US10310977B2 (en) 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using a processor cache
US10489273B2 (en) 2016-10-20 2019-11-26 Microsoft Technology Licensing, Llc Reuse of a related thread's cache while recording a trace file of code execution
US10540250B2 (en) 2016-11-11 2020-01-21 Microsoft Technology Licensing, Llc Reducing storage requirements for storing memory addresses and values
US10997048B2 (en) * 2016-12-30 2021-05-04 Intel Corporation Apparatus and method for multithreading-aware performance monitoring events
US10318332B2 (en) 2017-04-01 2019-06-11 Microsoft Technology Licensing, Llc Virtual machine execution tracing
US10296442B2 (en) 2017-06-29 2019-05-21 Microsoft Technology Licensing, Llc Distributed time-travel trace recording and replay
US10459824B2 (en) 2017-09-18 2019-10-29 Microsoft Technology Licensing, Llc Cache-based trace recording using cache coherence protocol data
US10558572B2 (en) 2018-01-16 2020-02-11 Microsoft Technology Licensing, Llc Decoupling trace data streams using cache coherence protocol data
US11907091B2 (en) 2018-02-16 2024-02-20 Microsoft Technology Licensing, Llc Trace recording by logging influxes to an upper-layer shared cache, plus cache coherence protocol transitions among lower-layer caches
US10496537B2 (en) 2018-02-23 2019-12-03 Microsoft Technology Licensing, Llc Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache
US10642737B2 (en) 2018-02-23 2020-05-05 Microsoft Technology Licensing, Llc Logging cache influxes by request to a higher-level cache
CN111209155B (zh) * 2018-11-21 2022-09-23 华夏芯(北京)通用处理器技术有限公司 一种便于扩展和配置的性能检测方法
US20240045725A1 (en) * 2022-08-04 2024-02-08 Intel Corporation Apparatus and Method for Concurrent Performance Monitoring per Compute Hardware Context
CN117472721B (zh) * 2023-12-28 2024-03-12 北京微核芯科技有限公司 事件统计方法及装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1686450A1 (ru) * 1989-07-26 1991-10-23 Конструкторское бюро автоматических систем Устройство дл контрол операций ввода-вывода
US5524250A (en) 1991-08-23 1996-06-04 Silicon Graphics, Inc. Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers
US5657253A (en) 1992-05-15 1997-08-12 Intel Corporation Apparatus for monitoring the performance of a microprocessor
US5557548A (en) 1994-12-09 1996-09-17 International Business Machines Corporation Method and system for performance monitoring within a data processing system
US5752062A (en) 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5796637A (en) * 1996-09-06 1998-08-18 Intel Corporation Apparatus and method for filtering event signals
US5938760A (en) 1996-12-17 1999-08-17 International Business Machines Corporation System and method for performance monitoring of instructions in a re-order buffer
US5796939A (en) 1997-03-10 1998-08-18 Digital Equipment Corporation High frequency sampling of processor performance counters
US5835705A (en) 1997-03-11 1998-11-10 International Business Machines Corporation Method and system for performance per-thread monitoring in a multithreaded processor
US6112318A (en) * 1997-08-11 2000-08-29 Digital Equipment Corporation Performance counters controlled by programmable logic
US6023759A (en) * 1997-09-30 2000-02-08 Intel Corporation System for observing internal processor events utilizing a pipeline data path to pipeline internally generated signals representative of the event
US6256775B1 (en) * 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6098169A (en) 1997-12-23 2000-08-01 Intel Corporation Thread performance analysis by monitoring processor performance event registers at thread switch
US6205468B1 (en) * 1998-03-10 2001-03-20 Lucent Technologies, Inc. System for multitasking management employing context controller having event vector selection by priority encoding of contex events
US6356615B1 (en) * 1999-10-13 2002-03-12 Transmeta Corporation Programmable event counter system

Also Published As

Publication number Publication date
KR100528151B1 (ko) 2005-11-15
RU2003122778A (ru) 2005-02-27
TW548593B (en) 2003-08-21
WO2002054245A3 (en) 2004-02-12
EP1407361A2 (de) 2004-04-14
KR20030063488A (ko) 2003-07-28
AU2002217850A1 (en) 2002-07-16
US7448025B2 (en) 2008-11-04
BR0116654A (pt) 2005-08-16
RU2268483C2 (ru) 2006-01-20
US20020124237A1 (en) 2002-09-05
WO2002054245A8 (en) 2002-09-12
EP1407361B1 (de) 2011-06-15
CN1500248A (zh) 2004-05-26
CN100492313C (zh) 2009-05-27
WO2002054245A2 (en) 2002-07-11

Similar Documents

Publication Publication Date Title
ATE513263T1 (de) Qualifizierung von ereigniserkennung durch thread-id und thread-privilegstufe
JP4034363B2 (ja) オペレーティング・システム・ベースのプログラムの性能モニタ方法およびシステム
KR870000115B1 (ko) 데이타 처리 시스템
ATE182223T1 (de) Verfahren und vorrichtung zur modellierung von rechnerprozessbetriebsmitteln
JPH07152611A (ja) エラー解析用のトレーサシステム
KR910017304A (ko) 데이타 처리방법 및 그 시스템
CN102184123B (zh) 一种附加地支持虚拟多线程的多线程处理器及系统
US20060048011A1 (en) Performance profiling of microprocessor systems using debug hardware and performance monitor
KR20140001887A (ko) 다중프로세서 시스템에서의 예외 제어
CN107168778A (zh) 一种任务处理方法及任务处理装置
JP2004252670A (ja) 共有リソースの競合検出器および共有リソースの競合検出方法
JPS60124746A (ja) デ−タ処理装置
JPS63289654A (ja) プログラム分岐命令モニタ方式
JPS6442742A (en) Fault monitoring method for multi-processor system
JPH05120081A (ja) 情報処理装置
JPH0566962A (ja) プログラムデバツグ方式
JPH0573361A (ja) マイクロコンピユータ
JPH01177647A (ja) 情報処理装置
JPS61183705A (ja) プログラマブルコントロ−ラの演算トレ−ス処理方法
JPS61233848A (ja) デバツグ装置
JPS57207952A (en) Instruction controlling system
JPS61166632A (ja) 割込み処理装置
JPS59221757A (ja) プログラムル−プ監視方式
JPS6015749A (ja) インラインtmp方式
JPS62229301A (ja) Cpuを用いた制御システムの暴走検知装置

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties