ATE509371T1 - Technik zur dimensionierung und plazierung von leistungsschaltern in einer integrierten schaltung - Google Patents
Technik zur dimensionierung und plazierung von leistungsschaltern in einer integrierten schaltungInfo
- Publication number
- ATE509371T1 ATE509371T1 AT04707972T AT04707972T ATE509371T1 AT E509371 T1 ATE509371 T1 AT E509371T1 AT 04707972 T AT04707972 T AT 04707972T AT 04707972 T AT04707972 T AT 04707972T AT E509371 T1 ATE509371 T1 AT E509371T1
- Authority
- AT
- Austria
- Prior art keywords
- switches
- dimensioning
- technology
- power
- power switches
- Prior art date
Links
- 230000001419 dependent effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/248,696 US6924661B2 (en) | 2003-02-10 | 2003-02-10 | Power switch circuit sizing technique |
| PCT/GB2004/000434 WO2004070773A2 (en) | 2003-02-10 | 2004-02-04 | Integrated circuit power switch circuit sizing and placement technique |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE509371T1 true ATE509371T1 (de) | 2011-05-15 |
Family
ID=32823584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT04707972T ATE509371T1 (de) | 2003-02-10 | 2004-02-04 | Technik zur dimensionierung und plazierung von leistungsschaltern in einer integrierten schaltung |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6924661B2 (de) |
| EP (1) | EP1593157B1 (de) |
| JP (1) | JP4566186B2 (de) |
| KR (1) | KR100734999B1 (de) |
| CN (1) | CN100370613C (de) |
| AT (1) | ATE509371T1 (de) |
| TW (1) | TWI276948B (de) |
| WO (1) | WO2004070773A2 (de) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3770836B2 (ja) * | 2002-01-23 | 2006-04-26 | 株式会社ルネサステクノロジ | 高速に電源スイッチのオンオフが可能な論理回路及び同論理回路における電流低減方法 |
| US8304813B2 (en) * | 2007-01-08 | 2012-11-06 | SanDisk Technologies, Inc. | Connection between an I/O region and the core region of an integrated circuit |
| JP4834625B2 (ja) * | 2007-07-31 | 2011-12-14 | 株式会社東芝 | 電源管理装置及び電源管理方法 |
| US7904838B2 (en) * | 2007-08-15 | 2011-03-08 | Ati Technologies Ulc | Circuits with transient isolation operable in a low power state |
| CN103577621B (zh) * | 2012-08-08 | 2017-06-23 | 扬智科技股份有限公司 | 晶片及其电源开关电路的布局方法 |
| JP2015069333A (ja) * | 2013-09-27 | 2015-04-13 | 富士通セミコンダクター株式会社 | 設計方法及び設計プログラム |
| US9058459B1 (en) * | 2013-12-30 | 2015-06-16 | Samsung Electronics Co., Ltd. | Integrated circuit layouts and methods to reduce leakage |
| US9824174B2 (en) * | 2015-09-11 | 2017-11-21 | Qualcomm Incorporated | Power-density-based clock cell spacing |
| CN111104771B (zh) * | 2018-10-26 | 2021-09-21 | 珠海格力电器股份有限公司 | 一种电源关断单元的摆放方法及装置 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52111389A (en) * | 1976-03-16 | 1977-09-19 | Nec Corp | Iil-type semi-conductor ic |
| JPH0817227B2 (ja) * | 1987-04-30 | 1996-02-21 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | 個性化可能な半導体チップ |
| US5256893A (en) * | 1987-07-22 | 1993-10-26 | Hitachi, Ltd. | Semiconductor integrated circuit device with power MOSFET incorporated |
| JPH0249449A (ja) * | 1989-06-23 | 1990-02-19 | Fujitsu Ltd | 半導体集積回路装置 |
| US5689428A (en) | 1990-09-28 | 1997-11-18 | Texas Instruments Incorporated | Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture |
| JPH0521713A (ja) * | 1991-07-09 | 1993-01-29 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| US5311058A (en) | 1991-11-29 | 1994-05-10 | Trw Inc. | Integrated circuit power distribution system |
| WO1995017007A1 (en) | 1993-12-14 | 1995-06-22 | Oki America, Inc. | Efficient routing method and resulting structure for integrated circuits |
| US5668389A (en) | 1994-12-02 | 1997-09-16 | Intel Corporation | Optimized power bus structure |
| JP3869045B2 (ja) | 1995-11-09 | 2007-01-17 | 株式会社日立製作所 | 半導体記憶装置 |
| US6091090A (en) | 1997-09-19 | 2000-07-18 | In-Chip Systems, Inc. | Power and signal routing technique for gate array design |
| US6072740A (en) | 1997-12-01 | 2000-06-06 | Intel Corporation | Apparatus for reducing the effects of power supply distribution related noise |
| JP4498500B2 (ja) * | 1999-10-06 | 2010-07-07 | 株式会社ルネサステクノロジ | 半導体装置 |
| US6396137B1 (en) * | 2000-03-15 | 2002-05-28 | Kevin Mark Klughart | Integrated voltage/current/power regulator/switch system and method |
| JP4963144B2 (ja) * | 2000-06-22 | 2012-06-27 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
| JP2002110802A (ja) * | 2000-09-27 | 2002-04-12 | Toshiba Corp | 半導体装置、半導体装置のレイアウト装置、及び半導体装置のレイアウト方法 |
| JP2002297271A (ja) * | 2001-03-28 | 2002-10-11 | Toshiba Corp | 半導体装置 |
-
2003
- 2003-02-10 US US10/248,696 patent/US6924661B2/en not_active Expired - Lifetime
-
2004
- 2004-02-02 TW TW093102341A patent/TWI276948B/zh not_active IP Right Cessation
- 2004-02-04 KR KR1020057012783A patent/KR100734999B1/ko active IP Right Grant
- 2004-02-04 JP JP2006502234A patent/JP4566186B2/ja not_active Expired - Fee Related
- 2004-02-04 CN CNB2004800016818A patent/CN100370613C/zh not_active Expired - Lifetime
- 2004-02-04 EP EP04707972A patent/EP1593157B1/de not_active Expired - Lifetime
- 2004-02-04 WO PCT/GB2004/000434 patent/WO2004070773A2/en active Search and Examination
- 2004-02-04 AT AT04707972T patent/ATE509371T1/de not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TWI276948B (en) | 2007-03-21 |
| JP2006518936A (ja) | 2006-08-17 |
| JP4566186B2 (ja) | 2010-10-20 |
| US20040155681A1 (en) | 2004-08-12 |
| TW200502744A (en) | 2005-01-16 |
| CN100370613C (zh) | 2008-02-20 |
| US6924661B2 (en) | 2005-08-02 |
| WO2004070773A2 (en) | 2004-08-19 |
| EP1593157B1 (de) | 2011-05-11 |
| CN1723561A (zh) | 2006-01-18 |
| KR20050092038A (ko) | 2005-09-16 |
| WO2004070773A3 (en) | 2004-10-28 |
| EP1593157A2 (de) | 2005-11-09 |
| KR100734999B1 (ko) | 2007-07-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |