ATE495498T1 - Integrierter schaltkreis und elektronische vorrichtung - Google Patents

Integrierter schaltkreis und elektronische vorrichtung

Info

Publication number
ATE495498T1
ATE495498T1 AT08710021T AT08710021T ATE495498T1 AT E495498 T1 ATE495498 T1 AT E495498T1 AT 08710021 T AT08710021 T AT 08710021T AT 08710021 T AT08710021 T AT 08710021T AT E495498 T1 ATE495498 T1 AT E495498T1
Authority
AT
Austria
Prior art keywords
conductors
pair
conductor
address
bus
Prior art date
Application number
AT08710021T
Other languages
English (en)
Inventor
Mihai Vitanescu
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE495498T1 publication Critical patent/ATE495498T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0052—Assignment of addresses or identifiers to the modules of a bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Credit Cards Or The Like (AREA)
AT08710021T 2007-02-19 2008-02-13 Integrierter schaltkreis und elektronische vorrichtung ATE495498T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07102663 2007-02-19
PCT/IB2008/050521 WO2008102284A1 (en) 2007-02-19 2008-02-13 Integrated circuit and electronic device

Publications (1)

Publication Number Publication Date
ATE495498T1 true ATE495498T1 (de) 2011-01-15

Family

ID=39434271

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08710021T ATE495498T1 (de) 2007-02-19 2008-02-13 Integrierter schaltkreis und elektronische vorrichtung

Country Status (6)

Country Link
US (1) US8112569B2 (de)
EP (1) EP2115606B1 (de)
CN (1) CN101617301B (de)
AT (1) ATE495498T1 (de)
DE (1) DE602008004447D1 (de)
WO (1) WO2008102284A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202372971U (zh) * 2010-11-29 2012-08-08 意法半导体股份有限公司 电子设备和电子系统
FR2969451B1 (fr) * 2010-12-17 2013-01-11 St Microelectronics Rousset Procede et dispositif de communication entre un maitre et plusieurs esclaves suivant un protocole de communication serie, en particulier du type a drain ouvert
CN103580678B (zh) * 2013-11-04 2016-08-17 复旦大学 一种基于fgpa的高性能查找表电路
US9710423B2 (en) * 2014-04-02 2017-07-18 Qualcomm Incorporated Methods to send extra information in-band on inter-integrated circuit (I2C) bus
GB2543324A (en) * 2015-10-14 2017-04-19 Vodafone Automotive S P A Automatic setting of identifiers for a plurality of identical electronic components in an array
CN113987991B (zh) * 2021-09-29 2022-09-27 展讯半导体(南京)有限公司 信号传输装置及电子设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6745270B1 (en) 2001-01-31 2004-06-01 International Business Machines Corporation Dynamically allocating I2C addresses using self bus switching device
US6954810B2 (en) 2003-06-30 2005-10-11 Lsi Logic Corporation Transparent switch
US7231467B2 (en) 2003-11-17 2007-06-12 Agere Systems Inc. Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput
EP1877916B1 (de) * 2005-04-29 2010-02-17 Nxp B.V. Dynamischer 12c-slave-einrichtungs-adressendecoder

Also Published As

Publication number Publication date
US8112569B2 (en) 2012-02-07
WO2008102284A1 (en) 2008-08-28
EP2115606A1 (de) 2009-11-11
CN101617301B (zh) 2011-12-14
DE602008004447D1 (de) 2011-02-24
CN101617301A (zh) 2009-12-30
EP2115606B1 (de) 2011-01-12
US20100030936A1 (en) 2010-02-04

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties