ATE479144T1 - Verteilter versand mit einem konkurrierenden ungeordneten versand - Google Patents

Verteilter versand mit einem konkurrierenden ungeordneten versand

Info

Publication number
ATE479144T1
ATE479144T1 AT08725539T AT08725539T ATE479144T1 AT E479144 T1 ATE479144 T1 AT E479144T1 AT 08725539 T AT08725539 T AT 08725539T AT 08725539 T AT08725539 T AT 08725539T AT E479144 T1 ATE479144 T1 AT E479144T1
Authority
AT
Austria
Prior art keywords
shipping
slots
instruction
unordered
competing
Prior art date
Application number
AT08725539T
Other languages
English (en)
Inventor
Gene Shen
Sean Lie
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE479144T1 publication Critical patent/ATE479144T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Developing Agents For Electrophotography (AREA)
  • Eye Examination Apparatus (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
AT08725539T 2007-02-13 2008-02-13 Verteilter versand mit einem konkurrierenden ungeordneten versand ATE479144T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/674,562 US7725690B2 (en) 2007-02-13 2007-02-13 Distributed dispatch with concurrent, out-of-order dispatch
PCT/US2008/001924 WO2008100551A1 (en) 2007-02-13 2008-02-13 Distributed dispatch with concurrent, out-of-order dispatch

Publications (1)

Publication Number Publication Date
ATE479144T1 true ATE479144T1 (de) 2010-09-15

Family

ID=39400404

Family Applications (2)

Application Number Title Priority Date Filing Date
AT10163124T ATE550713T1 (de) 2007-02-13 2008-02-13 Verteilter versand mit einem konkurrierenden ungeordneten versand
AT08725539T ATE479144T1 (de) 2007-02-13 2008-02-13 Verteilter versand mit einem konkurrierenden ungeordneten versand

Family Applications Before (1)

Application Number Title Priority Date Filing Date
AT10163124T ATE550713T1 (de) 2007-02-13 2008-02-13 Verteilter versand mit einem konkurrierenden ungeordneten versand

Country Status (8)

Country Link
US (1) US7725690B2 (de)
EP (2) EP2221718B1 (de)
KR (1) KR101466934B1 (de)
CN (1) CN101730880B (de)
AT (2) ATE550713T1 (de)
DE (1) DE602008002325D1 (de)
TW (1) TWI457827B (de)
WO (1) WO2008100551A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8533721B2 (en) * 2010-03-26 2013-09-10 Intel Corporation Method and system of scheduling out-of-order operations without the requirement to execute compare, ready and pick logic in a single cycle
US9529594B2 (en) 2010-11-30 2016-12-27 Oracle International Corporation Miss buffer for a multi-threaded processor
US10346173B2 (en) 2011-03-07 2019-07-09 Oracle International Corporation Multi-threaded instruction buffer design
US10223112B2 (en) 2011-12-22 2019-03-05 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
CN104011646B (zh) * 2011-12-22 2018-03-27 英特尔公司 用于产生按照数值顺序的连续整数的序列的处理器、方法、系统和指令
US10866807B2 (en) 2011-12-22 2020-12-15 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride
US20130166882A1 (en) * 2011-12-22 2013-06-27 Jack Hilaire Choquette Methods and apparatus for scheduling instructions without instruction decode

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69429061T2 (de) * 1993-10-29 2002-07-18 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5870578A (en) 1997-12-09 1999-02-09 Advanced Micro Devices, Inc. Workload balancing in a microprocessor for reduced instruction dispatch stalling
US6032249A (en) * 1998-02-02 2000-02-29 International Business Machines Corporation Method and system for executing a serializing instruction while bypassing a floating point unit pipeline
US6065110A (en) * 1998-02-09 2000-05-16 International Business Machines Corporation Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue
US6212621B1 (en) 1998-06-24 2001-04-03 Advanced Micro Devices Inc Method and system using tagged instructions to allow out-of-program-order instruction decoding
US6192465B1 (en) 1998-09-21 2001-02-20 Advanced Micro Devices, Inc. Using multiple decoders and a reorder queue to decode instructions out of order
US6622236B1 (en) * 2000-02-17 2003-09-16 International Business Machines Corporation Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions
US6785802B1 (en) 2000-06-01 2004-08-31 Stmicroelectronics, Inc. Method and apparatus for priority tracking in an out-of-order instruction shelf of a high performance superscalar microprocessor
US6826704B1 (en) * 2001-03-08 2004-11-30 Advanced Micro Devices, Inc. Microprocessor employing a performance throttling mechanism for power management
US6970999B2 (en) * 2002-07-31 2005-11-29 International Business Machines Corporation Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters
US7590824B2 (en) 2005-03-29 2009-09-15 Qualcomm Incorporated Mixed superscalar and VLIW instruction issuing and processing method and system

Also Published As

Publication number Publication date
CN101730880A (zh) 2010-06-09
EP2221718A2 (de) 2010-08-25
US7725690B2 (en) 2010-05-25
EP2122462B1 (de) 2010-08-25
DE602008002325D1 (de) 2010-10-07
KR101466934B1 (ko) 2014-12-01
KR20090113884A (ko) 2009-11-02
US20080195846A1 (en) 2008-08-14
ATE550713T1 (de) 2012-04-15
TW200841236A (en) 2008-10-16
EP2122462A1 (de) 2009-11-25
TWI457827B (zh) 2014-10-21
CN101730880B (zh) 2013-04-10
EP2221718A3 (de) 2010-11-10
WO2008100551A1 (en) 2008-08-21
EP2221718B1 (de) 2012-03-21

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