ATE500548T1 - Verfahren und vorrichtung zur längendecodierung und identifizierung von anweisungen variabler länge - Google Patents

Verfahren und vorrichtung zur längendecodierung und identifizierung von anweisungen variabler länge

Info

Publication number
ATE500548T1
ATE500548T1 AT08780088T AT08780088T ATE500548T1 AT E500548 T1 ATE500548 T1 AT E500548T1 AT 08780088 T AT08780088 T AT 08780088T AT 08780088 T AT08780088 T AT 08780088T AT E500548 T1 ATE500548 T1 AT E500548T1
Authority
AT
Austria
Prior art keywords
variable length
instruction
pointer
instructions
length
Prior art date
Application number
AT08780088T
Other languages
English (en)
Inventor
Gene Shen
Sean Lie
Original Assignee
Globalfoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Inc filed Critical Globalfoundries Inc
Application granted granted Critical
Publication of ATE500548T1 publication Critical patent/ATE500548T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Executing Machine-Instructions (AREA)
  • Image Processing (AREA)
AT08780088T 2007-07-10 2008-07-10 Verfahren und vorrichtung zur längendecodierung und identifizierung von anweisungen variabler länge ATE500548T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/775,456 US7818543B2 (en) 2007-07-10 2007-07-10 Method and apparatus for length decoding and identifying boundaries of variable length instructions
PCT/US2008/008466 WO2009009093A1 (en) 2007-07-10 2008-07-10 Method and apparatus for length decoding and identifying boundaries of variable length instructions

Publications (1)

Publication Number Publication Date
ATE500548T1 true ATE500548T1 (de) 2011-03-15

Family

ID=39766907

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08780088T ATE500548T1 (de) 2007-07-10 2008-07-10 Verfahren und vorrichtung zur längendecodierung und identifizierung von anweisungen variabler länge

Country Status (6)

Country Link
US (1) US7818543B2 (de)
EP (1) EP2176740B1 (de)
AT (1) ATE500548T1 (de)
DE (1) DE602008005315D1 (de)
TW (1) TW200912740A (de)
WO (1) WO2009009093A1 (de)

Families Citing this family (24)

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US9354890B1 (en) 2007-10-23 2016-05-31 Marvell International Ltd. Call stack structure for enabling execution of code outside of a subroutine and between call stack frames
US8095775B1 (en) * 2007-11-21 2012-01-10 Marvell International Ltd. Instruction pointers in very long instruction words
US9442758B1 (en) 2008-01-21 2016-09-13 Marvell International Ltd. Dynamic processor core switching
US9582443B1 (en) 2010-02-12 2017-02-28 Marvell International Ltd. Serial control channel processor for executing time-based instructions
US8884920B1 (en) 2011-05-25 2014-11-11 Marvell International Ltd. Programmatic sensing of capacitive sensors
US9098694B1 (en) 2011-07-06 2015-08-04 Marvell International Ltd. Clone-resistant logic
US9069553B2 (en) 2011-09-06 2015-06-30 Marvell World Trade Ltd. Switching tasks between heterogeneous cores
US8756591B2 (en) 2011-10-03 2014-06-17 International Business Machines Corporation Generating compiled code that indicates register liveness
US9329869B2 (en) 2011-10-03 2016-05-03 International Business Machines Corporation Prefix computer instruction for compatibily extending instruction functionality
US8615745B2 (en) 2011-10-03 2013-12-24 International Business Machines Corporation Compiling code for an enhanced application binary interface (ABI) with decode time instruction optimization
US10078515B2 (en) 2011-10-03 2018-09-18 International Business Machines Corporation Tracking operand liveness information in a computer system and performing function based on the liveness information
US9690583B2 (en) 2011-10-03 2017-06-27 International Business Machines Corporation Exploiting an architected list-use operand indication in a computer system operand resource pool
US9697002B2 (en) 2011-10-03 2017-07-04 International Business Machines Corporation Computer instructions for activating and deactivating operands
US8612959B2 (en) 2011-10-03 2013-12-17 International Business Machines Corporation Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization
US9354874B2 (en) 2011-10-03 2016-05-31 International Business Machines Corporation Scalable decode-time instruction sequence optimization of dependent instructions
US9286072B2 (en) 2011-10-03 2016-03-15 International Business Machines Corporation Using register last use infomation to perform decode-time computer instruction optimization
WO2013101031A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
US10761852B2 (en) 2015-09-30 2020-09-01 International Business Machines Corporation Extending data range addressing
US10394568B2 (en) * 2015-09-30 2019-08-27 International Business Machines Corporation Exception handling for applications with prefix instructions
US10877759B2 (en) 2015-09-30 2020-12-29 International Business Machines Corporation Managing the capture of information in applications with prefix instructions
WO2019046716A1 (en) * 2017-08-31 2019-03-07 MIPS Tech, LLC CONTROLLED INSTRUMENT PROCESSING BY POINTER SIZE
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537629A (en) * 1994-03-01 1996-07-16 Intel Corporation Decoder for single cycle decoding of single prefixes in variable length instructions
US5832249A (en) * 1995-01-25 1998-11-03 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5819057A (en) * 1995-01-25 1998-10-06 Advanced Micro Devices, Inc. Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units
US6006324A (en) * 1995-01-25 1999-12-21 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5822558A (en) 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5819056A (en) * 1995-10-06 1998-10-06 Advanced Micro Devices, Inc. Instruction buffer organization method and system
US5845099A (en) 1996-06-28 1998-12-01 Intel Corporation Length detecting unit for parallel processing of variable sequential instructions
US5948096A (en) 1997-12-23 1999-09-07 Intel Corporation Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes
US6260134B1 (en) 1998-11-02 2001-07-10 Advanced Micro Devices, Inc. Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte
US6405303B1 (en) * 1999-08-31 2002-06-11 Advanced Micro Devices, Inc. Massively parallel decoding and execution of variable-length instructions

Also Published As

Publication number Publication date
US7818543B2 (en) 2010-10-19
EP2176740A1 (de) 2010-04-21
WO2009009093A1 (en) 2009-01-15
DE602008005315D1 (de) 2011-04-14
TW200912740A (en) 2009-03-16
EP2176740B1 (de) 2011-03-02
US20090019257A1 (en) 2009-01-15

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