ATE468606T1 - Herstellungsverfahren für dünne schichten auf einem spezifischen substrat und anwendung - Google Patents

Herstellungsverfahren für dünne schichten auf einem spezifischen substrat und anwendung

Info

Publication number
ATE468606T1
ATE468606T1 AT02708436T AT02708436T ATE468606T1 AT E468606 T1 ATE468606 T1 AT E468606T1 AT 02708436 T AT02708436 T AT 02708436T AT 02708436 T AT02708436 T AT 02708436T AT E468606 T1 ATE468606 T1 AT E468606T1
Authority
AT
Austria
Prior art keywords
layer
application
production process
thin layers
embrittled
Prior art date
Application number
AT02708436T
Other languages
German (de)
English (en)
Inventor
Bernard Aspar
Jean-Frederic Clerc
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE468606T1 publication Critical patent/ATE468606T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/22—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement by transferring layers from a donor substrate to a final substrate utilising a temporary handle substrate as an intermediary
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor

Landscapes

  • Thin Film Transistor (AREA)
  • Laminated Bodies (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
  • Glass Compositions (AREA)
AT02708436T 2001-03-02 2002-03-01 Herstellungsverfahren für dünne schichten auf einem spezifischen substrat und anwendung ATE468606T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0102890A FR2821697B1 (fr) 2001-03-02 2001-03-02 Procede de fabrication de couches minces sur un support specifique et une application
PCT/FR2002/000754 WO2002071475A1 (fr) 2001-03-02 2002-03-01 Procede de fabrication de couches minces sur un support specifique et une application

Publications (1)

Publication Number Publication Date
ATE468606T1 true ATE468606T1 (de) 2010-06-15

Family

ID=8860683

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02708436T ATE468606T1 (de) 2001-03-02 2002-03-01 Herstellungsverfahren für dünne schichten auf einem spezifischen substrat und anwendung

Country Status (7)

Country Link
US (1) US6939782B2 (https=)
EP (1) EP1364400B9 (https=)
JP (1) JP4384410B2 (https=)
AT (1) ATE468606T1 (https=)
DE (1) DE60236410D1 (https=)
FR (1) FR2821697B1 (https=)
WO (1) WO2002071475A1 (https=)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839385B1 (fr) * 2002-05-02 2004-07-23 Soitec Silicon On Insulator Procede de decollement de couches de materiau
FR2874455B1 (fr) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
US6759277B1 (en) * 2003-02-27 2004-07-06 Sharp Laboratories Of America, Inc. Crystalline silicon die array and method for assembling crystalline silicon sheets onto substrates
US7309446B1 (en) * 2004-02-25 2007-12-18 Metadigm Llc Methods of manufacturing diamond capsules
FR2866983B1 (fr) * 2004-03-01 2006-05-26 Soitec Silicon On Insulator Realisation d'une entite en materiau semiconducteur sur substrat
EP1571705A3 (fr) * 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Réalisation d'une entité en matériau semiconducteur sur substrat
KR101152141B1 (ko) * 2005-06-08 2012-06-15 삼성전자주식회사 액정표시패널과 액정표시패널의 제조방법
WO2007019487A2 (en) * 2005-08-05 2007-02-15 Reveo, Inc. Method and system for fabricating thin devices
FR2935537B1 (fr) 2008-08-28 2010-10-22 Soitec Silicon On Insulator Procede d'initiation d'adhesion moleculaire
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2943177B1 (fr) * 2009-03-12 2011-05-06 Soitec Silicon On Insulator Procede de fabrication d'une structure multicouche avec report de couche circuit
FR2947380B1 (fr) 2009-06-26 2012-12-14 Soitec Silicon Insulator Technologies Procede de collage par adhesion moleculaire.
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
JP5480321B2 (ja) 2012-03-21 2014-04-23 株式会社東芝 磁気メモリ及びその製造方法
CN104507853B (zh) 2012-07-31 2016-11-23 索泰克公司 形成半导体设备的方法
FR2995136B1 (fr) * 2012-09-04 2015-06-26 Soitec Silicon On Insulator Pseudo-substrat avec efficacite amelioree d'utilisation d'un materiau monocristallin
US9209142B1 (en) * 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
WO2025226300A1 (en) * 2024-04-23 2025-10-30 Microchip Technology Incorporated Method including an ion beam implant and stressed film for separating a substrate film region from a bulk substrate region

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300788A (en) * 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
JPH07504764A (ja) * 1992-03-13 1995-05-25 コピン・コーポレーシヨン 頭部取り付け表示系
FR2715501B1 (fr) * 1994-01-26 1996-04-05 Commissariat Energie Atomique Procédé de dépôt de lames semiconductrices sur un support.
JP3352340B2 (ja) * 1995-10-06 2002-12-03 キヤノン株式会社 半導体基体とその製造方法
FR2744285B1 (fr) * 1996-01-25 1998-03-06 Commissariat Energie Atomique Procede de transfert d'une couche mince d'un substrat initial sur un substrat final
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US6127199A (en) * 1996-11-12 2000-10-03 Seiko Epson Corporation Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH11233449A (ja) * 1998-02-13 1999-08-27 Denso Corp 半導体基板の製造方法
JP3809733B2 (ja) * 1998-02-25 2006-08-16 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
JP4085459B2 (ja) * 1998-03-02 2008-05-14 セイコーエプソン株式会社 ３次元デバイスの製造方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
FR2795866B1 (fr) * 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'une membrane mince et structure a membrane ainsi obtenue
JP3804349B2 (ja) * 1999-08-06 2006-08-02 セイコーエプソン株式会社 薄膜デバイス装置の製造方法、アクティブマトリクス基板の製造方法、および電気光学装置
EP1939932A1 (en) * 1999-08-10 2008-07-02 Silicon Genesis Corporation A substrate comprising a stressed silicon germanium cleave layer

Also Published As

Publication number Publication date
FR2821697B1 (fr) 2004-06-25
EP1364400A1 (fr) 2003-11-26
WO2002071475A1 (fr) 2002-09-12
FR2821697A1 (fr) 2002-09-06
US6939782B2 (en) 2005-09-06
JP2004532515A (ja) 2004-10-21
JP4384410B2 (ja) 2009-12-16
US20040110320A1 (en) 2004-06-10
DE60236410D1 (de) 2010-07-01
EP1364400B9 (fr) 2012-03-21
EP1364400B1 (fr) 2010-05-19

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