ATE447209T1 - Fifo-speicherbaustein mit nichtflüchtiger speicherstufe - Google Patents
Fifo-speicherbaustein mit nichtflüchtiger speicherstufeInfo
- Publication number
- ATE447209T1 ATE447209T1 AT05702914T AT05702914T ATE447209T1 AT E447209 T1 ATE447209 T1 AT E447209T1 AT 05702914 T AT05702914 T AT 05702914T AT 05702914 T AT05702914 T AT 05702914T AT E447209 T1 ATE447209 T1 AT E447209T1
- Authority
- AT
- Austria
- Prior art keywords
- fifo
- memory device
- volatile
- fifo memory
- volatile memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Communication Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04100526 | 2004-02-12 | ||
PCT/IB2005/050489 WO2005078572A1 (en) | 2004-02-12 | 2005-02-08 | A fifo memory device with non-volatile storage stage |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE447209T1 true ATE447209T1 (de) | 2009-11-15 |
Family
ID=34854686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT05702914T ATE447209T1 (de) | 2004-02-12 | 2005-02-08 | Fifo-speicherbaustein mit nichtflüchtiger speicherstufe |
Country Status (8)
Country | Link |
---|---|
US (1) | US7489567B2 (de) |
EP (1) | EP1714210B1 (de) |
JP (1) | JP4576391B2 (de) |
KR (1) | KR20070003923A (de) |
CN (1) | CN1918541A (de) |
AT (1) | ATE447209T1 (de) |
DE (1) | DE602005017360D1 (de) |
WO (1) | WO2005078572A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060031565A1 (en) * | 2004-07-16 | 2006-02-09 | Sundar Iyer | High speed packet-buffering system |
KR100859989B1 (ko) | 2006-11-21 | 2008-09-25 | 한양대학교 산학협력단 | 플래시 메모리의 공간정보 관리장치 및 그 방법 |
US8122168B2 (en) * | 2007-05-17 | 2012-02-21 | International Business Machines Corporation | Method for implementing concurrent producer-consumer buffers |
JP5684016B2 (ja) * | 2011-03-23 | 2015-03-11 | 株式会社日立情報通信エンジニアリング | 入退管理制御装置、及び入退管理システム |
CN103575273A (zh) * | 2013-03-25 | 2014-02-12 | 西安电子科技大学 | 具有双缓存结构的光子脉冲到达时间读出装置 |
US10372413B2 (en) | 2016-09-18 | 2019-08-06 | International Business Machines Corporation | First-in-first-out buffer |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH083956B2 (ja) * | 1986-09-18 | 1996-01-17 | 日本テキサス・インスツルメンツ株式会社 | 半導体記憶装置 |
DE69124946T2 (de) * | 1990-11-30 | 1997-09-18 | Ibm | Bidirektionaler FIFO-Puffer zur Schnittstellenbildung zwischen zwei Bussen |
US5353248A (en) | 1992-04-14 | 1994-10-04 | Altera Corporation | EEPROM-backed FIFO memory |
GB2276739A (en) * | 1993-03-30 | 1994-10-05 | Ibm | System for storing persistent and non-persistent queued data. |
KR960014169B1 (ko) * | 1994-05-17 | 1996-10-14 | 금성일렉트론 주식회사 | 메모리의 데이타 입출력 상태 검출 회로 |
DE19650993A1 (de) * | 1996-11-26 | 1998-05-28 | Francotyp Postalia Gmbh | Anordnung und Verfahren zur Verbesserung der Datensicherheit mittels Ringpuffer |
US6678201B2 (en) * | 2002-04-08 | 2004-01-13 | Micron Technology, Inc. | Distributed FIFO in synchronous memory |
-
2005
- 2005-02-08 DE DE602005017360T patent/DE602005017360D1/de active Active
- 2005-02-08 US US10/589,114 patent/US7489567B2/en active Active
- 2005-02-08 AT AT05702914T patent/ATE447209T1/de not_active IP Right Cessation
- 2005-02-08 CN CNA2005800046697A patent/CN1918541A/zh active Pending
- 2005-02-08 WO PCT/IB2005/050489 patent/WO2005078572A1/en active Application Filing
- 2005-02-08 EP EP05702914A patent/EP1714210B1/de active Active
- 2005-02-08 KR KR1020067018560A patent/KR20070003923A/ko active IP Right Grant
- 2005-02-08 JP JP2006552746A patent/JP4576391B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
EP1714210B1 (de) | 2009-10-28 |
EP1714210A1 (de) | 2006-10-25 |
US7489567B2 (en) | 2009-02-10 |
JP2007522579A (ja) | 2007-08-09 |
CN1918541A (zh) | 2007-02-21 |
JP4576391B2 (ja) | 2010-11-04 |
KR20070003923A (ko) | 2007-01-05 |
WO2005078572A1 (en) | 2005-08-25 |
DE602005017360D1 (de) | 2009-12-10 |
US20070223265A1 (en) | 2007-09-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |