ATE445188T1 - Kommunikation in einem gatterprozessor - Google Patents

Kommunikation in einem gatterprozessor

Info

Publication number
ATE445188T1
ATE445188T1 AT04712607T AT04712607T ATE445188T1 AT E445188 T1 ATE445188 T1 AT E445188T1 AT 04712607 T AT04712607 T AT 04712607T AT 04712607 T AT04712607 T AT 04712607T AT E445188 T1 ATE445188 T1 AT E445188T1
Authority
AT
Austria
Prior art keywords
data
slot
processor
receiving
communication
Prior art date
Application number
AT04712607T
Other languages
English (en)
Inventor
Gajinder Panesar
Anthony Claydon
William Robbins
Alex Orr
Andrew Duller
Original Assignee
Picochip Designs Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Picochip Designs Ltd filed Critical Picochip Designs Ltd
Application granted granted Critical
Publication of ATE445188T1 publication Critical patent/ATE445188T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17393—Indirect interconnection networks non hierarchical topologies having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Multimedia (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Radio Relay Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Plural Heterocyclic Compounds (AREA)
AT04712607T 2003-02-21 2004-02-19 Kommunikation in einem gatterprozessor ATE445188T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0304055A GB2398650B (en) 2003-02-21 2003-02-21 Communications in a processor array
PCT/GB2004/000673 WO2004074963A2 (en) 2003-02-21 2004-02-19 Communications in a processor array

Publications (1)

Publication Number Publication Date
ATE445188T1 true ATE445188T1 (de) 2009-10-15

Family

ID=9953469

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04712607T ATE445188T1 (de) 2003-02-21 2004-02-19 Kommunikation in einem gatterprozessor

Country Status (9)

Country Link
US (1) US7987340B2 (de)
EP (1) EP1595216B1 (de)
JP (1) JP4455580B2 (de)
KR (1) KR101067593B1 (de)
CN (1) CN100414534C (de)
AT (1) ATE445188T1 (de)
DE (1) DE602004023482D1 (de)
GB (1) GB2398650B (de)
WO (1) WO2004074963A2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008049869A (ja) 2006-08-25 2008-03-06 Toyota Motor Corp レセプタクル
US11042211B2 (en) 2009-08-07 2021-06-22 Advanced Processor Architectures, Llc Serially connected computing nodes in a distributed computing system
US9429983B1 (en) 2013-09-12 2016-08-30 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US8675371B2 (en) 2009-08-07 2014-03-18 Advanced Processor Architectures, Llc Distributed computing
US9645603B1 (en) 2013-09-12 2017-05-09 Advanced Processor Architectures, Llc System clock distribution in a distributed computing environment
US8260992B2 (en) * 2010-04-12 2012-09-04 Advanced Micro Devices, Inc. Reducing simultaneous switching outputs using data bus inversion signaling
US9071740B1 (en) 2011-10-28 2015-06-30 Google Inc. Modular camera system
US9537968B1 (en) 2012-01-06 2017-01-03 Google Inc. Communication of socket protocol based data over a storage protocol based interface
US9197686B1 (en) * 2012-01-06 2015-11-24 Google Inc. Backfill of video stream
CN105379394A (zh) * 2014-03-11 2016-03-02 华为技术有限公司 一种应答消息传输装置与方法
WO2015140842A1 (ja) * 2014-03-20 2015-09-24 日本電気株式会社 システムを監視する情報処理装置及び監視方法
US9544485B2 (en) 2015-05-27 2017-01-10 Google Inc. Multi-mode LED illumination system
US9235899B1 (en) 2015-06-12 2016-01-12 Google Inc. Simulating an infrared emitter array in a video monitoring camera to construct a lookup table for depth determination
US9886620B2 (en) 2015-06-12 2018-02-06 Google Llc Using a scene illuminating infrared emitter array in a video monitoring camera to estimate the position of the camera
US9386230B1 (en) 2015-06-12 2016-07-05 Google Inc. Day and night detection based on one or more of illuminant detection, lux level detection, and tiling
US9454820B1 (en) 2015-06-12 2016-09-27 Google Inc. Using a scene illuminating infrared emitter array in a video monitoring camera for depth determination
US9613423B2 (en) 2015-06-12 2017-04-04 Google Inc. Using a depth map of a monitored scene to identify floors, walls, and ceilings
US9554063B2 (en) 2015-06-12 2017-01-24 Google Inc. Using infrared images of a monitored scene to identify windows
US9626849B2 (en) 2015-06-12 2017-04-18 Google Inc. Using scene information from a security camera to reduce false security alerts
US9489745B1 (en) 2015-06-12 2016-11-08 Google Inc. Using depth maps of a scene to identify movement of a video camera
US10180615B2 (en) 2016-10-31 2019-01-15 Google Llc Electrochromic filtering in a camera

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698746A (en) * 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
US4914653A (en) * 1986-12-22 1990-04-03 American Telephone And Telegraph Company Inter-processor communication protocol
EP0428770B1 (de) * 1989-11-21 1995-02-01 Deutsche ITT Industries GmbH Datengesteuerter Arrayprozessor
JP2601591B2 (ja) * 1991-11-26 1997-04-16 富士通株式会社 並列計算機およびその全対全通信方法
JP3461520B2 (ja) * 1992-11-30 2003-10-27 富士通株式会社 マルチプロセッサシステム
US5754807A (en) 1995-11-20 1998-05-19 Advanced Micro Devices, Inc. Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles
US6424870B1 (en) * 1996-02-09 2002-07-23 Hitachi, Ltd. Parallel processor
US5959995A (en) * 1996-02-22 1999-09-28 Fujitsu, Ltd. Asynchronous packet switching
US5802561A (en) * 1996-06-28 1998-09-01 Digital Equipment Corporation Simultaneous, mirror write cache
GB2370380B (en) * 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
US7161978B2 (en) * 2001-08-29 2007-01-09 Texas Instruments Incorporated Transmit and receive window synchronization

Also Published As

Publication number Publication date
CN1751305A (zh) 2006-03-22
WO2004074963A2 (en) 2004-09-02
EP1595216B1 (de) 2009-10-07
KR101067593B1 (ko) 2011-09-27
WO2004074963A3 (en) 2005-01-27
JP2006519429A (ja) 2006-08-24
JP4455580B2 (ja) 2010-04-21
US20070083791A1 (en) 2007-04-12
KR20050115865A (ko) 2005-12-08
GB2398650A (en) 2004-08-25
US7987340B2 (en) 2011-07-26
EP1595216A2 (de) 2005-11-16
GB2398650B (en) 2006-09-20
CN100414534C (zh) 2008-08-27
DE602004023482D1 (de) 2009-11-19
GB0304055D0 (en) 2003-03-26

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