ATE436050T1 - Pipeline-asynchron-anweisungs-prozessorschaltun - Google Patents

Pipeline-asynchron-anweisungs-prozessorschaltun

Info

Publication number
ATE436050T1
ATE436050T1 AT05732298T AT05732298T ATE436050T1 AT E436050 T1 ATE436050 T1 AT E436050T1 AT 05732298 T AT05732298 T AT 05732298T AT 05732298 T AT05732298 T AT 05732298T AT E436050 T1 ATE436050 T1 AT E436050T1
Authority
AT
Austria
Prior art keywords
stages
write
dependent information
pipeline
writing
Prior art date
Application number
AT05732298T
Other languages
English (en)
Inventor
Adrianus Bink
Clercq Mark De
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE436050T1 publication Critical patent/ATE436050T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3871—Asynchronous instruction pipeline, e.g. using handshake signals between stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AT05732298T 2004-04-27 2005-04-21 Pipeline-asynchron-anweisungs-prozessorschaltun ATE436050T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04101748 2004-04-27
PCT/IB2005/051312 WO2005103885A2 (en) 2004-04-27 2005-04-21 Pipelined asynchronous instruction processor circuit

Publications (1)

Publication Number Publication Date
ATE436050T1 true ATE436050T1 (de) 2009-07-15

Family

ID=34965452

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05732298T ATE436050T1 (de) 2004-04-27 2005-04-21 Pipeline-asynchron-anweisungs-prozessorschaltun

Country Status (7)

Country Link
US (1) US7484078B2 (de)
EP (1) EP1745367B1 (de)
JP (1) JP2007535060A (de)
CN (1) CN100437472C (de)
AT (1) ATE436050T1 (de)
DE (1) DE602005015313D1 (de)
WO (1) WO2005103885A2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7873953B1 (en) * 2006-01-20 2011-01-18 Altera Corporation High-level language code sequence optimization for implementing programmable chip designs
JP2010500641A (ja) * 2006-08-08 2010-01-07 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子装置及び通信同期方法
US8566482B2 (en) * 2011-01-04 2013-10-22 Icron Technologies Corporation Method and system for communicating DisplayPort and single-link DVI/HDMI information for dual-mode devices
US20150082006A1 (en) * 2013-09-06 2015-03-19 Futurewei Technologies, Inc. System and Method for an Asynchronous Processor with Asynchronous Instruction Fetch, Decode, and Issue
US20150074353A1 (en) * 2013-09-06 2015-03-12 Futurewei Technologies, Inc. System and Method for an Asynchronous Processor with Multiple Threading
US10318305B2 (en) * 2013-09-06 2019-06-11 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with pepelined arithmetic and logic unit
WO2015035339A1 (en) * 2013-09-06 2015-03-12 Huawei Technologies Co., Ltd. System and method for an asynchronous processor with heterogeneous processors
US9552456B2 (en) * 2015-05-29 2017-01-24 Altera Corporation Methods and apparatus for probing signals from a circuit after register retiming
CN114765455A (zh) * 2021-01-14 2022-07-19 深圳比特微电子科技有限公司 处理器和计算系统
CN117827285B (zh) * 2024-03-04 2024-06-14 芯来智融半导体科技(上海)有限公司 向量处理器访存指令缓存方法、系统、设备及存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
GB9114513D0 (en) * 1991-07-04 1991-08-21 Univ Manchester Condition detection in asynchronous pipelines
JP3338488B2 (ja) * 1992-11-18 2002-10-28 富士通株式会社 データ処理装置の検証方法及び装置
US5553276A (en) * 1993-06-30 1996-09-03 International Business Machines Corporation Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units
US6088788A (en) * 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
AU8495098A (en) * 1997-07-16 1999-02-10 California Institute Of Technology Improved devices and methods for asynchronous processing
US6301655B1 (en) * 1997-09-15 2001-10-09 California Institute Of Technology Exception processing in asynchronous processor

Also Published As

Publication number Publication date
US20080040581A1 (en) 2008-02-14
CN1950796A (zh) 2007-04-18
EP1745367B1 (de) 2009-07-08
WO2005103885A2 (en) 2005-11-03
JP2007535060A (ja) 2007-11-29
DE602005015313D1 (de) 2009-08-20
US7484078B2 (en) 2009-01-27
WO2005103885A3 (en) 2006-08-24
CN100437472C (zh) 2008-11-26
EP1745367A2 (de) 2007-01-24

Similar Documents

Publication Publication Date Title
ATE436050T1 (de) Pipeline-asynchron-anweisungs-prozessorschaltun
JP3698838B2 (ja) 動的論理パイプライン制御
EP0820010B1 (de) Verfahren zur Schätzung des Leistungsverbrauchs eines Mikroprozessors
EP2145273B1 (de) Berechnung des phasenverhältnis durch abstasten des taktgebers
US8612726B2 (en) Multi-cycle programmable processor with FSM implemented controller selectively altering functional units datapaths based on instruction type
ATE416418T1 (de) Register für datenuebertragung in einem multithreaded prozessor
US20050267732A1 (en) Method of visualization in processor based emulation system
Topiwala et al. Implementation of a 32-bit MIPS based RISC processor using Cadence
KR920020315A (ko) 병렬프로세서
JP2004519041A (ja) 効率的なデータロード及びアンロードのために統合されるパケット基準のプロトコル論理を用いるハードウェア支援設計検証システム
Stepchenkov et al. Energy efficient speed-independent 64-bit fused multiply-add unit
DE602005019180D1 (de) Datenverarbeitungsschaltung mit funktionseinheiten mit gemeinsamen leseports
US8516421B1 (en) Generating circuit design properties from signal traces
CN100530103C (zh) 一种模拟器及方法
Reaz et al. A single clock cycle MIPS RISC processor design using VHDL
US8909994B2 (en) Dynamic hardware trace supporting multiphase operations
Scherer et al. An out-of-order three-way superscalar multimedia floating-point unit
CN114217856A (zh) 面向AArch64架构的CPU指令微基准测试方法及系统
KR100439073B1 (ko) 기능 평가 기능을 구비한 반도체 장치
JP6473023B2 (ja) 性能評価モジュール及びこれを組み込んだ半導体集積回路
JP2003216411A5 (de)
Beyer et al. The application of formal technology on fixed-point arithmetic systemC designs
TW201510721A (zh) 時序分析方法以及機器可讀媒體
Brej Blame passing for analysis and optimisation
Tu et al. A high-speed Baugh-Wooley multiplier design using skew-tolerant domino techniques

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties