ATE432497T1 - System und verfahren zur adaptiven optimierung des tastverhältnisses - Google Patents

System und verfahren zur adaptiven optimierung des tastverhältnisses

Info

Publication number
ATE432497T1
ATE432497T1 AT04756590T AT04756590T ATE432497T1 AT E432497 T1 ATE432497 T1 AT E432497T1 AT 04756590 T AT04756590 T AT 04756590T AT 04756590 T AT04756590 T AT 04756590T AT E432497 T1 ATE432497 T1 AT E432497T1
Authority
AT
Austria
Prior art keywords
duty cycle
receiver
data signal
clock
signal received
Prior art date
Application number
AT04756590T
Other languages
English (en)
Inventor
Huy Nguyen
Roxanne Vu
Leung Yu
Benedict Lau
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of ATE432497T1 publication Critical patent/ATE432497T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
  • Mobile Radio Communication Systems (AREA)
AT04756590T 2003-09-12 2004-06-29 System und verfahren zur adaptiven optimierung des tastverhältnisses ATE432497T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/661,225 US7307461B2 (en) 2003-09-12 2003-09-12 System and method for adaptive duty cycle optimization
PCT/US2004/021368 WO2005036399A1 (en) 2003-09-12 2004-06-29 System and method for adaptive duty cycle optimization

Publications (1)

Publication Number Publication Date
ATE432497T1 true ATE432497T1 (de) 2009-06-15

Family

ID=34273829

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04756590T ATE432497T1 (de) 2003-09-12 2004-06-29 System und verfahren zur adaptiven optimierung des tastverhältnisses

Country Status (5)

Country Link
US (1) US7307461B2 (de)
EP (1) EP1668510B1 (de)
AT (1) ATE432497T1 (de)
DE (1) DE602004021274D1 (de)
WO (1) WO2005036399A1 (de)

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US7307461B2 (en) 2003-09-12 2007-12-11 Rambus Inc. System and method for adaptive duty cycle optimization
US20060002493A1 (en) * 2004-06-30 2006-01-05 Infineon Technologies Ag Method and device for generating a duty cycle related output signal
US7469354B2 (en) * 2005-04-21 2008-12-23 Infineon Technologies Ag Circuit including a deskew circuit for asymmetrically delaying rising and falling edges
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US7489176B2 (en) * 2006-04-28 2009-02-10 Rambus Inc. Clock distribution circuit
KR100808591B1 (ko) * 2006-06-30 2008-02-29 주식회사 하이닉스반도체 클럭 트리 회로 및 그를 이용한 듀티 보정 테스트 방법과그를 포함하는 반도체 메모리 장치
KR100763849B1 (ko) * 2006-08-10 2007-10-05 삼성전자주식회사 멀티 위상 클럭 신호들간의 위상 스큐를 감소시키는 위상보정 회로, 그 방법 및 상기 회로를 구비하는 반도체 장치
KR100771887B1 (ko) * 2006-10-17 2007-11-01 삼성전자주식회사 듀티 검출기 및 이를 구비하는 듀티 검출/보정 회로
US7764734B2 (en) * 2006-10-31 2010-07-27 Winbond Electronics Corporation Digital pulse width modulation with variable period and error distribution
US7667512B2 (en) * 2007-03-29 2010-02-23 Standard Microsystems Corporation Duty cycle comparator
US8767696B2 (en) * 2007-07-23 2014-07-01 The Boeing Company System and method for media access control for a duty cycle network
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US7821315B2 (en) * 2007-11-08 2010-10-26 Qualcomm Incorporated Adjustable duty cycle circuit
US7609583B2 (en) * 2007-11-12 2009-10-27 Micron Technology, Inc. Selective edge phase mixing
US7839194B2 (en) * 2007-11-21 2010-11-23 Rambus Inc. Clock circuitry for generating multiple clocks with time-multiplexed duty cycle adjustment
TW200926133A (en) * 2007-12-14 2009-06-16 Realtek Semiconductor Corp Display processing device and timing controller
US8615205B2 (en) 2007-12-18 2013-12-24 Qualcomm Incorporated I-Q mismatch calibration and method
US8125259B2 (en) * 2008-01-03 2012-02-28 Agere Systems Inc. Duty cycle distortion (DCD) jitter modeling, calibration and generation methods
KR20090089500A (ko) * 2008-02-19 2009-08-24 주식회사 하이닉스반도체 듀티 싸이클 보정 회로
US8970272B2 (en) 2008-05-15 2015-03-03 Qualcomm Incorporated High-speed low-power latches
US9367711B1 (en) * 2008-09-04 2016-06-14 Intelleflex Corporation Battery assisted RFID tag with square-law receiver and optional part time active behavior
US8161313B2 (en) 2008-09-30 2012-04-17 Mosaid Technologies Incorporated Serial-connected memory system with duty cycle correction
EP2329496A4 (de) * 2008-09-30 2012-06-13 Mosaid Technologies Inc Seriell geschaltetes speichersystem mit ausgabeverzögerungseinstellung
US8181056B2 (en) 2008-09-30 2012-05-15 Mosaid Technologies Incorporated Serial-connected memory system with output delay adjustment
US8712357B2 (en) 2008-11-13 2014-04-29 Qualcomm Incorporated LO generation with deskewed input oscillator signal
US8718574B2 (en) 2008-11-25 2014-05-06 Qualcomm Incorporated Duty cycle adjustment for a local oscillator signal
JP5231289B2 (ja) * 2009-03-02 2013-07-10 ルネサスエレクトロニクス株式会社 デューティ比補正回路及びデューティ比補正方法
KR101006088B1 (ko) * 2009-06-04 2011-01-06 주식회사 하이닉스반도체 데이터 전달의 신뢰성을 보장하기 위한 반도체 메모리 장치 및 이를 포함하는 반도체 시스템
US8847638B2 (en) 2009-07-02 2014-09-30 Qualcomm Incorporated High speed divide-by-two circuit
US8791740B2 (en) 2009-07-16 2014-07-29 Qualcomm Incorporated Systems and methods for reducing average current consumption in a local oscillator path
KR101239709B1 (ko) * 2010-10-29 2013-03-06 에스케이하이닉스 주식회사 반도체 메모리 장치의 듀티 사이클 보정 회로
US8854098B2 (en) 2011-01-21 2014-10-07 Qualcomm Incorporated System for I-Q phase mismatch detection and correction
US8665665B2 (en) * 2011-03-30 2014-03-04 Mediatek Inc. Apparatus and method to adjust clock duty cycle of memory
US8817914B2 (en) * 2011-08-26 2014-08-26 Nanya Technology Corporation Interactive digital duty cycle compensation circuit for receiver
US8432208B2 (en) * 2011-09-28 2013-04-30 Microchip Technology Incorporated Maintaining pulse width modulation data-set coherency
US8432207B1 (en) 2011-12-30 2013-04-30 Advanced Micro Devices, Inc. Method and apparatus for correcting the duty cycle of a high speed clock
EP2807663A4 (de) * 2012-01-23 2015-06-24 Univ Utah State Doppelte seitliche steuerung für induktive leistungsübertragung
US9154077B2 (en) 2012-04-12 2015-10-06 Qualcomm Incorporated Compact high frequency divider
US9148135B2 (en) * 2012-06-26 2015-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Real time automatic and background calibration at embedded duty cycle correlation
EP2787640A1 (de) 2013-04-05 2014-10-08 Technische Universität Darmstadt Programmierbare Weitbereichs-Arbeitszykluskorrektur
JP6476659B2 (ja) * 2014-08-28 2019-03-06 富士通株式会社 信号再生回路および信号再生方法
US11064433B2 (en) 2017-03-15 2021-07-13 Carrier Corporation Wireless event notification system having a wireless device configured to communicate at dynamically configurable frequencies
US10923175B2 (en) 2018-01-31 2021-02-16 Samsung Electronics Co., Ltd. Memory device adjusting duty cycle and memory system having the same
KR102473661B1 (ko) * 2018-01-31 2022-12-02 삼성전자주식회사 듀티 사이클을 조절하는 메모리 장치 및 이를 포함하는 메모리 시스템
US10833656B2 (en) * 2018-04-30 2020-11-10 Micron Technology, Inc. Autonomous duty cycle calibration
EP3648348B1 (de) * 2018-10-29 2022-09-28 NXP USA, Inc. Arbeitszyklusüberwachungsschaltung und verfahren zur arbeitszyklusüberwachung

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US6125157A (en) 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JP3072833B2 (ja) 1997-05-23 2000-08-07 日本電気株式会社 ディジタルｐｌｌ回路
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US6016282A (en) 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6862296B1 (en) * 1999-12-21 2005-03-01 Lsi Logic Corporation Receive deserializer circuit for framing parallel data
EP1314249A2 (de) * 2000-09-01 2003-05-28 Honeywell International Inc. Hochgenauer synchroner spannung-frequenzwandler mit mehreren kanälen
US7298807B2 (en) 2003-02-11 2007-11-20 Rambus Inc. Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data
US7307461B2 (en) 2003-09-12 2007-12-11 Rambus Inc. System and method for adaptive duty cycle optimization

Also Published As

Publication number Publication date
DE602004021274D1 (de) 2009-07-09
US7307461B2 (en) 2007-12-11
US20050058233A1 (en) 2005-03-17
EP1668510A1 (de) 2006-06-14
WO2005036399A1 (en) 2005-04-21
EP1668510B1 (de) 2009-05-27

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