ATE431590T1 - Verfahren zum dynamischen einstellen einer speicherseitenschliess-strategie - Google Patents

Verfahren zum dynamischen einstellen einer speicherseitenschliess-strategie

Info

Publication number
ATE431590T1
ATE431590T1 AT02794434T AT02794434T ATE431590T1 AT E431590 T1 ATE431590 T1 AT E431590T1 AT 02794434 T AT02794434 T AT 02794434T AT 02794434 T AT02794434 T AT 02794434T AT E431590 T1 ATE431590 T1 AT E431590T1
Authority
AT
Austria
Prior art keywords
memory
page
accesses
set point
dynamically adjusting
Prior art date
Application number
AT02794434T
Other languages
English (en)
Inventor
Opher D Khan
Jeffrey R Wilcox
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE431590T1 publication Critical patent/ATE431590T1/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT02794434T 2002-01-03 2002-12-27 Verfahren zum dynamischen einstellen einer speicherseitenschliess-strategie ATE431590T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/039,087 US6799241B2 (en) 2002-01-03 2002-01-03 Method for dynamically adjusting a memory page closing policy
PCT/US2002/041550 WO2003058456A1 (en) 2002-01-03 2002-12-27 Method for dynamically adjusting a memory page closing policy

Publications (1)

Publication Number Publication Date
ATE431590T1 true ATE431590T1 (de) 2009-05-15

Family

ID=21903596

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02794434T ATE431590T1 (de) 2002-01-03 2002-12-27 Verfahren zum dynamischen einstellen einer speicherseitenschliess-strategie

Country Status (9)

Country Link
US (1) US6799241B2 (de)
EP (1) EP1461706B1 (de)
KR (1) KR100626770B1 (de)
CN (1) CN1284086C (de)
AT (1) ATE431590T1 (de)
AU (1) AU2002359868A1 (de)
DE (1) DE60232367D1 (de)
TW (1) TWI284261B (de)
WO (1) WO2003058456A1 (de)

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Also Published As

Publication number Publication date
US20030126354A1 (en) 2003-07-03
AU2002359868A1 (en) 2003-07-24
WO2003058456A1 (en) 2003-07-17
KR20040064742A (ko) 2004-07-19
US6799241B2 (en) 2004-09-28
KR100626770B1 (ko) 2006-09-25
EP1461706A1 (de) 2004-09-29
DE60232367D1 (de) 2009-06-25
CN1284086C (zh) 2006-11-08
TW200305803A (en) 2003-11-01
EP1461706B1 (de) 2009-05-13
CN1613064A (zh) 2005-05-04
TWI284261B (en) 2007-07-21

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