ATE398307T1 - Verfahren und vorrichtung zur verminderung der taktsignalverschiebung in einem muster-slave system mit mehreren verborgen taktzyklen - Google Patents

Verfahren und vorrichtung zur verminderung der taktsignalverschiebung in einem muster-slave system mit mehreren verborgen taktzyklen

Info

Publication number
ATE398307T1
ATE398307T1 AT00932161T AT00932161T ATE398307T1 AT E398307 T1 ATE398307 T1 AT E398307T1 AT 00932161 T AT00932161 T AT 00932161T AT 00932161 T AT00932161 T AT 00932161T AT E398307 T1 ATE398307 T1 AT E398307T1
Authority
AT
Austria
Prior art keywords
master
slave
path
clock
clock signal
Prior art date
Application number
AT00932161T
Other languages
English (en)
Inventor
Donald Perino
Haw-Jyh Liaw
Kevin Donnelly
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of ATE398307T1 publication Critical patent/ATE398307T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Control Of Stepping Motors (AREA)
  • Electric Clocks (AREA)
AT00932161T 1999-05-07 2000-05-08 Verfahren und vorrichtung zur verminderung der taktsignalverschiebung in einem muster-slave system mit mehreren verborgen taktzyklen ATE398307T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/306,897 US6426984B1 (en) 1999-05-07 1999-05-07 Apparatus and method for reducing clock signal phase skew in a master-slave system with multiple latent clock cycles

Publications (1)

Publication Number Publication Date
ATE398307T1 true ATE398307T1 (de) 2008-07-15

Family

ID=23187351

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00932161T ATE398307T1 (de) 1999-05-07 2000-05-08 Verfahren und vorrichtung zur verminderung der taktsignalverschiebung in einem muster-slave system mit mehreren verborgen taktzyklen

Country Status (5)

Country Link
US (1) US6426984B1 (de)
EP (1) EP1095481B1 (de)
AT (1) ATE398307T1 (de)
DE (1) DE60039153D1 (de)
WO (1) WO2000069109A1 (de)

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US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
US6646953B1 (en) * 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US6643787B1 (en) 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6647506B1 (en) * 1999-11-30 2003-11-11 Integrated Memory Logic, Inc. Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle
US6987823B1 (en) * 2000-02-07 2006-01-17 Rambus Inc. System and method for aligning internal transmit and receive clocks
US6968024B1 (en) * 2000-08-01 2005-11-22 Rambus Inc. Apparatus and method for operating a master-slave system with a clock signal and a separate phase signal
US6745338B1 (en) * 2000-09-12 2004-06-01 Cypress Semiconductor Corp. System for automatically selecting clock modes based on a state of clock input pin and generating a clock signal with an oscillator thereafter
US6898726B1 (en) * 2000-11-15 2005-05-24 Micron Technology, Inc. Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations
DE10148878B4 (de) * 2001-10-04 2006-03-02 Siemens Ag System und Verfahren zum Übertragen digitaler Daten
KR100454126B1 (ko) * 2002-01-15 2004-10-26 삼성전자주식회사 분리된 클록 라인을 구비한 정보 처리 시스템
US7073001B1 (en) * 2002-04-03 2006-07-04 Applied Micro Circuits Corporation Fault-tolerant digital communications channel having synchronized unidirectional links
US7130367B1 (en) * 2002-04-09 2006-10-31 Applied Micro Circuits Corporation Digital delay lock loop for setup and hold time enhancement
US7245975B2 (en) * 2005-04-20 2007-07-17 Parker-Hannifin Corporation Skew compensation
US7512201B2 (en) * 2005-06-14 2009-03-31 International Business Machines Corporation Multi-channel synchronization architecture
US7487378B2 (en) * 2005-09-19 2009-02-03 Ati Technologies, Inc. Asymmetrical IO method and system
US7375569B2 (en) * 2005-09-21 2008-05-20 Leco Corporation Last stage synchronizer system
US7983373B2 (en) * 2007-02-07 2011-07-19 Vintomie Networks B.V., Llc Clock distribution for 10GBase-T analog front end
US10135601B1 (en) * 2017-05-16 2018-11-20 Disney Enterprises, Inc. Providing common point of control and configuration in IP-based timing systems
US10333503B1 (en) 2018-11-26 2019-06-25 Quantum Machines Quantum controller with modular and dynamic pulse generation and routing
US10454459B1 (en) 2019-01-14 2019-10-22 Quantum Machines Quantum controller with multiple pulse modes
US10505524B1 (en) 2019-03-06 2019-12-10 Quantum Machines Synchronization in a quantum controller with modular and dynamic pulse generation and routing
US11164100B2 (en) 2019-05-02 2021-11-02 Quantum Machines Modular and dynamic digital control in a quantum controller
US10931267B1 (en) 2019-07-31 2021-02-23 Quantum Machines Frequency generation in a quantum controller
US10862465B1 (en) 2019-09-02 2020-12-08 Quantum Machines Quantum controller architecture
US11245390B2 (en) 2019-09-02 2022-02-08 Quantum Machines Software-defined pulse orchestration platform
US11043939B1 (en) 2020-08-05 2021-06-22 Quantum Machines Frequency management for quantum control
US20230153678A1 (en) * 2021-07-21 2023-05-18 Quantum Machines System and method for clock synchronization and time transfer between quantum orchestration platform elements
US12111352B2 (en) 2022-01-24 2024-10-08 Quantum Machines Machine learning for syncing multiple FPGA ports in a quantum system

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DE3751608T2 (de) * 1986-09-01 1996-06-27 Nippon Electric Co Serielles Busschnittstellensystem zur Datenübertragung mit einer Zweidrahtleitung als Taktbus und Datenbus.
CA1301261C (en) * 1988-04-27 1992-05-19 Wayne D. Grover Method and apparatus for clock distribution and for distributed clock synchronization
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5355391A (en) * 1992-03-06 1994-10-11 Rambus, Inc. High speed bus system
DE4390991T1 (de) 1992-03-06 1995-02-23 Rambus Inc Verfahren und Schaltungsanordnung zum Minimieren der Takt-Daten-Schieflage in einem Bussystem
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
JP3194314B2 (ja) * 1993-04-28 2001-07-30 ソニー株式会社 同期型回路
US5724392A (en) * 1993-10-04 1998-03-03 Siemens Business Communication Systems, Inc. Automatic path delay compensation system
US5625805A (en) * 1994-06-30 1997-04-29 Digital Equipment Corporation Clock architecture for synchronous system bus which regulates and adjusts clock skew
US5619158A (en) * 1995-08-18 1997-04-08 International Business Machines Corp. Hierarchical clocking system using adaptive feedback
US6233294B1 (en) * 1999-08-17 2001-05-15 Richard Bowers Method and apparatus for accomplishing high bandwidth serial communication between semiconductor devices

Also Published As

Publication number Publication date
DE60039153D1 (de) 2008-07-24
US6426984B1 (en) 2002-07-30
WO2000069109A1 (en) 2000-11-16
EP1095481A4 (de) 2005-12-28
EP1095481A1 (de) 2001-05-02
EP1095481B1 (de) 2008-06-11

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