ATE389208T1 - Assoziativspeicher zur cachespeicherung - Google Patents

Assoziativspeicher zur cachespeicherung

Info

Publication number
ATE389208T1
ATE389208T1 AT00955510T AT00955510T ATE389208T1 AT E389208 T1 ATE389208 T1 AT E389208T1 AT 00955510 T AT00955510 T AT 00955510T AT 00955510 T AT00955510 T AT 00955510T AT E389208 T1 ATE389208 T1 AT E389208T1
Authority
AT
Austria
Prior art keywords
data
associative memory
search
associative
caching
Prior art date
Application number
AT00955510T
Other languages
English (en)
Inventor
Alex Henderson
Walter Croft
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE389208T1 publication Critical patent/ATE389208T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
AT00955510T 1999-08-11 2000-08-11 Assoziativspeicher zur cachespeicherung ATE389208T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14840699P 1999-08-11 1999-08-11
US09/636,305 US6378042B1 (en) 1999-08-11 2000-08-10 Caching associative memory

Publications (1)

Publication Number Publication Date
ATE389208T1 true ATE389208T1 (de) 2008-03-15

Family

ID=26845830

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00955510T ATE389208T1 (de) 1999-08-11 2000-08-11 Assoziativspeicher zur cachespeicherung

Country Status (6)

Country Link
US (1) US6378042B1 (de)
EP (1) EP1212684B1 (de)
AT (1) ATE389208T1 (de)
AU (1) AU6770700A (de)
DE (1) DE60038307T2 (de)
WO (1) WO2001011469A1 (de)

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EP1667027A1 (de) 1999-09-07 2006-06-07 Intel Corporation Zwischenspeicherung (Caching) in dynamischem Speicher
JP4097883B2 (ja) * 2000-07-04 2008-06-11 松下電器産業株式会社 データ転送装置および方法
US20020049922A1 (en) * 2000-10-25 2002-04-25 Neocore Inc. Search engine system and method
US6775745B1 (en) * 2001-09-07 2004-08-10 Roxio, Inc. Method and apparatus for hybrid data caching mechanism
US6820170B1 (en) 2002-06-24 2004-11-16 Applied Micro Circuits Corporation Context based cache indexing
US7013367B2 (en) * 2002-07-18 2006-03-14 Intel Corporation Caching associative memory using non-overlapping data
JP2005190429A (ja) * 2003-12-26 2005-07-14 Hiroshima Univ 参照データ認識・学習方法及びパターン認識システム
US7392349B1 (en) * 2004-01-27 2008-06-24 Netlogic Microsystems, Inc. Table management within a policy-based routing system
US20060242368A1 (en) * 2005-04-26 2006-10-26 Cheng-Yen Huang Method of Queuing and Related Apparatus
US7502890B2 (en) * 2006-07-07 2009-03-10 International Business Machines Corporation Method and apparatus for dynamic priority-based cache replacement
US7870128B2 (en) * 2006-07-28 2011-01-11 Diskeeper Corporation Assigning data for storage based on speed with which data may be retrieved
US9052826B2 (en) * 2006-07-28 2015-06-09 Condusiv Technologies Corporation Selecting storage locations for storing data based on storage location attributes and data usage statistics
US20090132621A1 (en) * 2006-07-28 2009-05-21 Craig Jensen Selecting storage location for file storage based on storage longevity and speed
US8812533B1 (en) * 2009-05-21 2014-08-19 Salesforce.Com, Inc. System, method and computer program product for automatically presenting selectable options in a lookup field
US8438330B2 (en) 2010-05-17 2013-05-07 Netlogic Microsystems, Inc. Updating cam arrays using prefix length distribution prediction
US20120124291A1 (en) * 2010-11-16 2012-05-17 International Business Machines Corporation Secondary Cache Memory With A Counter For Determining Whether to Replace Cached Data
US9286237B2 (en) * 2013-03-11 2016-03-15 Intel Corporation Memory imbalance prediction based cache management
US20150039823A1 (en) * 2013-07-30 2015-02-05 Mediatek Inc. Table lookup apparatus using content-addressable memory based device and related table lookup method thereof

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US3911401A (en) 1973-06-04 1975-10-07 Ibm Hierarchial memory/storage system for an electronic computer
US4980823A (en) * 1987-06-22 1990-12-25 International Business Machines Corporation Sequential prefetching with deconfirmation
EP0496439B1 (de) * 1991-01-15 1998-01-21 Koninklijke Philips Electronics N.V. Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafür
US5265232A (en) * 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
US5761706A (en) * 1994-11-01 1998-06-02 Cray Research, Inc. Stream buffers for high-performance computer memory system
US5701426A (en) * 1995-03-31 1997-12-23 Bull Information Systems Inc. Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio
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US6065091A (en) * 1997-05-30 2000-05-16 Via-Cyrix, Inc. Translation look-aside buffer slice circuit and method of operation
US5970509A (en) * 1997-05-30 1999-10-19 National Semiconductor Corporation Hit determination circuit for selecting a data set based on miss determinations in other data sets and method of operation
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US6161144A (en) * 1998-01-23 2000-12-12 Alcatel Internetworking (Pe), Inc. Network switching device with concurrent key lookups
GB2348024B (en) * 1999-03-16 2003-06-25 Ibm Cache memory systems

Also Published As

Publication number Publication date
EP1212684A1 (de) 2002-06-12
DE60038307D1 (de) 2008-04-24
EP1212684B1 (de) 2008-03-12
WO2001011469A1 (en) 2001-02-15
AU6770700A (en) 2001-03-05
US6378042B1 (en) 2002-04-23
DE60038307T2 (de) 2009-03-19

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Legal Events

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