ATE369568T1 - Automatische testmustererzeugung - Google Patents

Automatische testmustererzeugung

Info

Publication number
ATE369568T1
ATE369568T1 AT04733894T AT04733894T ATE369568T1 AT E369568 T1 ATE369568 T1 AT E369568T1 AT 04733894 T AT04733894 T AT 04733894T AT 04733894 T AT04733894 T AT 04733894T AT E369568 T1 ATE369568 T1 AT E369568T1
Authority
AT
Austria
Prior art keywords
code words
test pattern
pattern generation
automatic test
test patterns
Prior art date
Application number
AT04733894T
Other languages
English (en)
Inventor
Erik Marinissen
Hubertus Vermeulen
Hendrik Hollmann
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE369568T1 publication Critical patent/ATE369568T1/de

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Holo Graphy (AREA)
  • Magnetic Heads (AREA)
  • Developing Agents For Electrophotography (AREA)
AT04733894T 2003-05-23 2004-05-19 Automatische testmustererzeugung ATE369568T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03076586A EP1480049A1 (de) 2003-05-23 2003-05-23 Automatische Testmuster-Erzeugung

Publications (1)

Publication Number Publication Date
ATE369568T1 true ATE369568T1 (de) 2007-08-15

Family

ID=33041024

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04733894T ATE369568T1 (de) 2003-05-23 2004-05-19 Automatische testmustererzeugung

Country Status (7)

Country Link
US (1) US20060259842A1 (de)
EP (2) EP1480049A1 (de)
JP (1) JP4694493B2 (de)
CN (1) CN100520428C (de)
AT (1) ATE369568T1 (de)
DE (1) DE602004008065T2 (de)
WO (1) WO2004104609A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7971119B2 (en) * 2005-09-29 2011-06-28 aiwan Semiconductor Manufacturing Company, Ltd. System and method for defect-based scan analysis
JP2010002370A (ja) * 2008-06-23 2010-01-07 Fujitsu Ltd パターン抽出プログラム、方法及び装置
EP4283875A1 (de) * 2022-05-24 2023-11-29 Siemens Aktiengesellschaft Verfahren zur überwachung einer mehrzahl kurzschlussbildender meldeelemente und anordnung zur durchführung des verfahrens

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636229A (en) * 1992-11-18 1997-06-03 U.S. Philips Corporation Method for generating test patterns to detect an electric shortcircuit, a method for testing electric circuitry while using test patterns so generated, and a tester device for testing electric circuitry with such test patterns
TW583405B (en) * 2002-12-23 2004-04-11 Via Tech Inc Signal detection method suitable for integrated circuit chip
JP2005172549A (ja) * 2003-12-10 2005-06-30 Matsushita Electric Ind Co Ltd 半導体集積回路の検証方法及びテストパターンの作成方法

Also Published As

Publication number Publication date
CN100520428C (zh) 2009-07-29
EP1480049A1 (de) 2004-11-24
CN1795394A (zh) 2006-06-28
DE602004008065T2 (de) 2008-04-17
US20060259842A1 (en) 2006-11-16
WO2004104609A1 (en) 2004-12-02
EP1629291B1 (de) 2007-08-08
DE602004008065D1 (de) 2007-09-20
JP4694493B2 (ja) 2011-06-08
EP1629291A1 (de) 2006-03-01
JP2007514131A (ja) 2007-05-31

Similar Documents

Publication Publication Date Title
ATE374950T1 (de) Automatische testmustererzeugung
JP5123214B2 (ja) メロディジェネレータ
ATE511678T1 (de) Verfahren zur verschleierung von datenstrukturen mittels deterministischer natürlicher datensubstitution
WO2005010932A3 (en) Mask network design for scan-based integrated circuits
DE60204556D1 (de) Taktsignalgenerator mit niedrigem jitter für ein test-system
NO20053897L (no) Sustem og fremgangsmate for automatisert plattformgenerering
TW200734822A (en) Positive resist composition and pattern forming method using the same
DE60032321D1 (de) System zur Erzeugung einer Bitfolge
DE60138082D1 (de) Bildverarbeitungsvorrichtung und Bildverarbeitungsverfahren
ATE386073T1 (de) Positiv arbeitende resistzusammensetzung und verfahren zur herstellung von mustern unter verwendung dieser zusammensetzung.
TW200520046A (en) Exposure method and exposure management system
NO20034455L (no) System for å generere pseudo-tilfeldige sekvenser
ATE531131T1 (de) Verfahren und vorrichtung zum verteilen mehrerer signaleingänge an mehrere integrierte schaltungen
ATE315257T1 (de) Vergleichen von mustern
US6990642B2 (en) Design method for integrated circuit having scan function
ATE369568T1 (de) Automatische testmustererzeugung
TWI263916B (en) System and method for reducing design cycle time for designing input/output cells
HK1097910A1 (en) Cdma integrated circuit demodulator with build-in test pattern generation
ATE333101T1 (de) Verfahren zur generierung von testersteuerungen
ATE403272T1 (de) Verfahren und elektrische vorrichtung für die leistungsfähige generierung von mehrfachraten- pseudozufallsfolgen
EP1162472A3 (de) Automatische Prüfmustererzeugung mit Zuweisungsentscheindung-Diagramm
ATE366912T1 (de) Verfahren und vorrichtung zur sprachausgabe, datenträger mit sprachdaten
ATE487178T1 (de) Erzeugung einer pseudozufälligen datensequenz
TW200615561A (en) Digital logic test method to systematically approach functional coverage completely and related apparatus and system
DE58903184D1 (de) Schaltungsanordung zur identifikation integrierter halbleiterschaltkreise.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties