ATE360252T1 - Speichermodulbaugruppe, die teilweise defekte chips verwendet - Google Patents

Speichermodulbaugruppe, die teilweise defekte chips verwendet

Info

Publication number
ATE360252T1
ATE360252T1 AT03713706T AT03713706T ATE360252T1 AT E360252 T1 ATE360252 T1 AT E360252T1 AT 03713706 T AT03713706 T AT 03713706T AT 03713706 T AT03713706 T AT 03713706T AT E360252 T1 ATE360252 T1 AT E360252T1
Authority
AT
Austria
Prior art keywords
partially
memory module
clock
module assembly
defective
Prior art date
Application number
AT03713706T
Other languages
English (en)
Inventor
Charles I Peddle
Original Assignee
Celetronix International Ltd
Celetronix Usa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Celetronix International Ltd, Celetronix Usa Inc filed Critical Celetronix International Ltd
Application granted granted Critical
Publication of ATE360252T1 publication Critical patent/ATE360252T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/88Masking faults in memories by using spares or by reconfiguring with partially good memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/88Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G11C29/886Masking faults in memories by using spares or by reconfiguring with partially good memories combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/029Programmable, customizable or modifiable circuits having a programmable lay-out, i.e. adapted for choosing between a few possibilities
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0292Programmable, customizable or modifiable circuits having a modifiable lay-out, i.e. adapted for engineering changes or repair
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/121Arrangements for protection of devices protecting against mechanical damage
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10159Memory
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/162Testing a finished product, e.g. heat cycle testing of solder joints
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/581Auxiliary members, e.g. flow barriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
AT03713706T 2002-02-26 2003-02-24 Speichermodulbaugruppe, die teilweise defekte chips verwendet ATE360252T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36003602P 2002-02-26 2002-02-26
US10/371,736 US20030161198A1 (en) 2002-02-26 2003-02-20 Method and apparatus for implementing a selectively operable clock booster for DDR memory or other logic modules which utilize partially-defective memory parts, or a combination of partially-defective and flawless memory parts

Publications (1)

Publication Number Publication Date
ATE360252T1 true ATE360252T1 (de) 2007-05-15

Family

ID=27760587

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03713706T ATE360252T1 (de) 2002-02-26 2003-02-24 Speichermodulbaugruppe, die teilweise defekte chips verwendet

Country Status (10)

Country Link
US (1) US20030161198A1 (de)
EP (2) EP1699056A1 (de)
KR (1) KR20050002834A (de)
AT (1) ATE360252T1 (de)
AU (1) AU2003217745A1 (de)
CA (1) CA2477754A1 (de)
DE (1) DE60313302T2 (de)
DK (1) DK1483722T3 (de)
ES (1) ES2283760T3 (de)
WO (1) WO2003073356A1 (de)

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0738274B2 (ja) * 1988-12-22 1995-04-26 株式会社東芝 不揮発性半導体メモリシステム
US4922128A (en) * 1989-01-13 1990-05-01 Ibm Corporation Boost clock circuit for driving redundant wordlines and sample wordlines
US5208178A (en) * 1990-08-02 1993-05-04 Hitachi, Ltd. Manufacturing a semiconductor integrated circuit device having on chip logic correction
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
JP3273440B2 (ja) * 1994-10-19 2002-04-08 マイクロン・テクノロジー・インコーポレーテッド 部分的に良好なメモリ集積回路から使用可能な部分を得るための効率的な方法
IN188196B (de) * 1995-05-15 2002-08-31 Silicon Graphics Inc
JPH09282900A (ja) * 1996-04-11 1997-10-31 Oki Electric Ind Co Ltd メモリモジュール
US6119049A (en) * 1996-08-12 2000-09-12 Tandon Associates, Inc. Memory module assembly using partially defective chips
US5867448A (en) * 1997-06-11 1999-02-02 Cypress Semiconductor Corp. Buffer for memory modules with trace delay compensation
US6351827B1 (en) * 1998-04-08 2002-02-26 Kingston Technology Co. Voltage and clock margin testing of memory-modules using an adapter board mounted to a PC motherboard
US6195762B1 (en) * 1998-06-24 2001-02-27 Micron Techonology, Inc. Circuit and method for masking a dormant memory cell
US6282210B1 (en) * 1998-08-12 2001-08-28 Staktek Group L.P. Clock driver with instantaneously selectable phase and method for use in data communication systems
JP4480855B2 (ja) * 2000-06-08 2010-06-16 富士通マイクロエレクトロニクス株式会社 半導体デバイスを含むモジュール、及びモジュールを含むシステム
US6445625B1 (en) * 2000-08-25 2002-09-03 Micron Technology, Inc. Memory device redundancy selection having test inputs
US6711695B1 (en) * 2001-01-26 2004-03-23 Hewlett-Packard Development Company, L.P. PECL voltage DIMM with remote multi-module etch skew compensation
US6763444B2 (en) * 2001-05-08 2004-07-13 Micron Technology, Inc. Read/write timing calibration of a memory array using a row or a redundant row

Also Published As

Publication number Publication date
AU2003217745A1 (en) 2003-09-09
EP1483722A1 (de) 2004-12-08
CA2477754A1 (en) 2003-09-04
DE60313302D1 (de) 2007-05-31
DE60313302T2 (de) 2008-01-03
WO2003073356A8 (en) 2004-07-29
EP1699056A1 (de) 2006-09-06
ES2283760T3 (es) 2007-11-01
US20030161198A1 (en) 2003-08-28
DK1483722T3 (da) 2007-06-25
EP1483722A4 (de) 2005-04-27
WO2003073356A1 (en) 2003-09-04
AU2003217745A8 (en) 2003-09-09
KR20050002834A (ko) 2005-01-10
EP1483722B1 (de) 2007-04-18

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