ATE349735T1 - Vorrichtung zur erhaltung der producer-consumer anordnung entlang einer ungeordneten schnittstelle - Google Patents

Vorrichtung zur erhaltung der producer-consumer anordnung entlang einer ungeordneten schnittstelle

Info

Publication number
ATE349735T1
ATE349735T1 AT02761228T AT02761228T ATE349735T1 AT E349735 T1 ATE349735 T1 AT E349735T1 AT 02761228 T AT02761228 T AT 02761228T AT 02761228 T AT02761228 T AT 02761228T AT E349735 T1 ATE349735 T1 AT E349735T1
Authority
AT
Austria
Prior art keywords
transactions
read
ioq
write
ooq
Prior art date
Application number
AT02761228T
Other languages
English (en)
Inventor
Kenneth Creta
Bradford Congdon
Deepak Ramachandran
Tony Rand
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE349735T1 publication Critical patent/ATE349735T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Display Devices Of Pinball Game Machines (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
AT02761228T 2001-08-27 2002-08-01 Vorrichtung zur erhaltung der producer-consumer anordnung entlang einer ungeordneten schnittstelle ATE349735T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/940,292 US6801976B2 (en) 2001-08-27 2001-08-27 Mechanism for preserving producer-consumer ordering across an unordered interface

Publications (1)

Publication Number Publication Date
ATE349735T1 true ATE349735T1 (de) 2007-01-15

Family

ID=25474578

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02761228T ATE349735T1 (de) 2001-08-27 2002-08-01 Vorrichtung zur erhaltung der producer-consumer anordnung entlang einer ungeordneten schnittstelle

Country Status (8)

Country Link
US (1) US6801976B2 (de)
EP (1) EP1421503B1 (de)
KR (1) KR100545952B1 (de)
CN (1) CN100432972C (de)
AT (1) ATE349735T1 (de)
DE (1) DE60217132T2 (de)
TW (1) TW571223B (de)
WO (1) WO2003019398A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6754734B2 (en) * 2001-12-18 2004-06-22 International Business Machines Corporation Systems, methods, and computer program products to improve performance of ported applications, such as a database
US6912612B2 (en) * 2002-02-25 2005-06-28 Intel Corporation Shared bypass bus structure
DE10234933A1 (de) * 2002-07-31 2004-03-18 Advanced Micro Devices, Inc., Sunnyvale Pufferung von Non-Posted-Lesebefehlen und Antworten
US6941407B2 (en) * 2002-09-27 2005-09-06 Hewlett-Packard Development Company, L.P. Method and apparatus for ordering interconnect transactions in a computer system
US7000060B2 (en) * 2002-09-27 2006-02-14 Hewlett-Packard Development Company, L.P. Method and apparatus for ordering interconnect transactions in a computer system
US6976142B1 (en) * 2003-05-07 2005-12-13 Agilent Technologies, Inc. Method and system to provide simultaneous access by multiple pipelines to a table
US7117287B2 (en) * 2003-05-30 2006-10-03 Sun Microsystems, Inc. History FIFO with bypass wherein an order through queue is maintained irrespective of retrieval of data
US7165131B2 (en) * 2004-04-27 2007-01-16 Intel Corporation Separating transactions into different virtual channels
US7346713B2 (en) * 2004-11-12 2008-03-18 International Business Machines Corporation Methods and apparatus for servicing commands through a memory controller port
GB0622408D0 (en) * 2006-11-10 2006-12-20 Ibm Device and method for detection and processing of stalled data request
US8607249B2 (en) * 2011-09-22 2013-12-10 Oracle International Corporation System and method for efficient concurrent queue implementation
US8689237B2 (en) 2011-09-22 2014-04-01 Oracle International Corporation Multi-lane concurrent bag for facilitating inter-thread communication
US8782356B2 (en) * 2011-12-09 2014-07-15 Qualcomm Incorporated Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions
US9755997B2 (en) 2012-01-13 2017-09-05 Intel Corporation Efficient peer-to-peer communication support in SoC fabrics
WO2013119212A1 (en) * 2012-02-07 2013-08-15 Intel Corporation Deterministic method to support multiple producers with multiple consumers in peer or hierarchical systems
CN103532875B (zh) * 2013-10-12 2017-11-03 丁贤根 一种用于pcie应用层接口的重排序方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5694556A (en) 1995-06-07 1997-12-02 International Business Machines Corporation Data processing system including buffering mechanism for inbound and outbound reads and posted writes
US5925099A (en) 1995-06-15 1999-07-20 Intel Corporation Method and apparatus for transporting messages between processors in a multiple processor system
US5828865A (en) 1995-12-27 1998-10-27 Intel Corporation Dual mode bus bridge for interfacing a host bus and a personal computer interface bus
US6243781B1 (en) 1998-12-03 2001-06-05 Intel Corporation Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe
US6219737B1 (en) 1998-12-10 2001-04-17 International Business Machines Corporation Read request performance of a multiple set buffer pool bus bridge

Also Published As

Publication number Publication date
EP1421503B1 (de) 2006-12-27
DE60217132D1 (de) 2007-02-08
EP1421503A1 (de) 2004-05-26
CN1575459A (zh) 2005-02-02
TW571223B (en) 2004-01-11
KR100545952B1 (ko) 2006-01-26
CN100432972C (zh) 2008-11-12
KR20040029448A (ko) 2004-04-06
WO2003019398A1 (en) 2003-03-06
US6801976B2 (en) 2004-10-05
DE60217132T2 (de) 2007-10-25
US20030041185A1 (en) 2003-02-27

Similar Documents

Publication Publication Date Title
ATE349735T1 (de) Vorrichtung zur erhaltung der producer-consumer anordnung entlang einer ungeordneten schnittstelle
NO20053752L (no) Middel for a kommunisere med USB smartkort ved bruk av fullhastighets eller hoyhastighets overforing.
CN105224482A (zh) 一种fpga加速卡高速存储系统
EP1199874A3 (de) Steuerungssystem und -Verfahren für digitale Abbildungvorrichtungen der Massenspeicherklasse
ATE424583T1 (de) Vorrichtung und verfahren zum unterstützen der speicherverwaltung in einem offload der netzwerkprotokollverarbeitung
WO2003042880A1 (fr) Appareil de traitement d'informations et procede associe, et systeme de traitement d'informations et procede associe
TWI376605B (en) Method and apparatus for enhancing data rate of advanced micro-controller bus architecture
WO2006124497A3 (en) Method and apparatus for payment without payment card infrastructure
WO2017000684A1 (zh) 一种数据读取方法、对端设备、控制器及存储介质
ATE428244T1 (de) Drahtloser usb-netzwerkadapter mit chipkarte
US20060129713A1 (en) Pipeline architecture for content creation for the portable media player from the internet
WO2017120739A1 (zh) 餐饮评论分析方法及系统
ATE298114T1 (de) Integriertes verkaufsstellen- und internet- vielfachanwendungssystem und verfahren zu dessen gebrauch
Karoubi et al. The role of electronic tourism in the development of medical tourism in Mashhad
CN203788300U (zh) 一种单向数据传输装置
Yong-cheng Design and implement of test system for extreme ultraviolet camera electronic control unit.
FR2865822B1 (fr) Dispositif de saisie, de consultation et de traitement de donnees, notamment medicales
CN218938952U (zh) 一种台式机主板去除南桥芯片结构
Umney New online live music agencies have oversized power over musicians
Xiaoru et al. Design and implementation of the universal rs232-gpib interface
CN205506198U (zh) 开有手机接口的称重装置
Erdem et al. Modeling arbitrary polynomial bispectra in one and two dimensions
JP2000215658A5 (de)
CN204515853U (zh) 健康查体信息记录仪
Chengting et al. Research on supersonic nozzle performance based on atomization effect evaluation.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties