ATE28765T1 - Intelligente prozessor-/speicher-elemente und systeme. - Google Patents

Intelligente prozessor-/speicher-elemente und systeme.

Info

Publication number
ATE28765T1
ATE28765T1 AT85200472T AT85200472T ATE28765T1 AT E28765 T1 ATE28765 T1 AT E28765T1 AT 85200472 T AT85200472 T AT 85200472T AT 85200472 T AT85200472 T AT 85200472T AT E28765 T1 ATE28765 T1 AT E28765T1
Authority
AT
Austria
Prior art keywords
elementary
basic
states
nary
storage
Prior art date
Application number
AT85200472T
Other languages
English (en)
Inventor
August Stern
Victor Stern
Original Assignee
August Stern
Victor Stern
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by August Stern, Victor Stern filed Critical August Stern
Application granted granted Critical
Publication of ATE28765T1 publication Critical patent/ATE28765T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Artificial Intelligence (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hardware Redundancy (AREA)
AT85200472T 1984-03-29 1985-03-29 Intelligente prozessor-/speicher-elemente und systeme. ATE28765T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8400984A NL8400984A (nl) 1984-03-29 1984-03-29 Elementaire component van een stelsel voor opslag en/of verwerking van informatie en stelsel met dergelijke elementaire componenten.
EP85200472A EP0166466B1 (de) 1984-03-29 1985-03-29 Intelligente Prozessor-/Speicher-Elemente und Systeme

Publications (1)

Publication Number Publication Date
ATE28765T1 true ATE28765T1 (de) 1987-08-15

Family

ID=19843718

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85200472T ATE28765T1 (de) 1984-03-29 1985-03-29 Intelligente prozessor-/speicher-elemente und systeme.

Country Status (4)

Country Link
EP (1) EP0166466B1 (de)
AT (1) ATE28765T1 (de)
DE (1) DE3560417D1 (de)
NL (1) NL8400984A (de)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2903413A1 (de) * 1979-01-30 1980-08-07 Paul Stefan Dr Puetter Elektrische schaltung mit lernfaehigkeit

Also Published As

Publication number Publication date
EP0166466A1 (de) 1986-01-02
NL8400984A (nl) 1985-10-16
DE3560417D1 (en) 1987-09-10
EP0166466B1 (de) 1987-08-05

Similar Documents

Publication Publication Date Title
Kasahara et al. Practical multiprocessor scheduling algorithms for efficient parallel processing
SU1420601A1 (ru) Вычислительна система
Thomassen Disjoint cycles in digraphs
KR880006612A (ko) 푸지 컴퓨터
ATE14250T1 (de) Mehrrechner-datenverarbeitungssystem.
James et al. A new characterization of the Dirichlet distribution through neutrality
CN103999035A (zh) 用于状态机中的数据分析的方法及系统
ATE28765T1 (de) Intelligente prozessor-/speicher-elemente und systeme.
US5379388A (en) Digital signal processing apparatus with sequencer designating program routines
Vaidya et al. Safe system level diagnosis
ESENWEIN VLDC string matching for associative computing and multiple broadcast mesh
Rakshit et al. An efficient tree-generation algorithm
EP0012242A1 (de) Digitaler Datenprozessor für wort- und zeichenorientierte Verarbeitung
Smith Generation of internal state assignments for large asynchronous sequential machines
Korobitsin On the complexity of domination number determination in monogenic classes of graphs
Betcke et al. ExCALIBUR—UK’s Preparation for the Arrival of the Next Generation of HPC
Wojciechowski Three families of integrable one-particle potentials
Kožešnik et al. Monte-Carlo methods from the point of view of algorithmic complexity
SU868768A1 (ru) Система дл решени задач математической физики
Datta et al. A graph theoretic approach for state assignment of asynchronous sequential machines
Chauvet Multiway Storage Modification Machines
Swartvagher et al. Rank Reordering within MPI Communicators to Exploit Deep Hierarchal Architectures of Supercomputers
Nakagawa et al. Discussion of" Optimization by Integer Programming of Constrained Reliability Problems with Several Modes of Failure''
SU970381A1 (ru) Устройство дл решени систем алгебраических уравнений
Dvořák MULTI-TERMINAL BDDS IN MICROPROCESSOR-BASED CONTROL

Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee