ATE278988T1 - Verfahren und vorrichtung zur schnittstellenbildung mit ram-speicher - Google Patents

Verfahren und vorrichtung zur schnittstellenbildung mit ram-speicher

Info

Publication number
ATE278988T1
ATE278988T1 AT00201754T AT00201754T ATE278988T1 AT E278988 T1 ATE278988 T1 AT E278988T1 AT 00201754 T AT00201754 T AT 00201754T AT 00201754 T AT00201754 T AT 00201754T AT E278988 T1 ATE278988 T1 AT E278988T1
Authority
AT
Austria
Prior art keywords
clock rate
sender
receiver
control
clock
Prior art date
Application number
AT00201754T
Other languages
English (en)
Inventor
Anthony Mark Jones
William Philip Robbins
Donald William Walke Patterson
Adrian Philip Wise
Helen Rosemary Finch
Martin William Sotheran
Stinchcombe
Original Assignee
Discovision Ass
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9405914A external-priority patent/GB9405914D0/en
Priority claimed from GB9415413A external-priority patent/GB9415413D0/en
Priority claimed from GB9415391A external-priority patent/GB9415391D0/en
Priority claimed from GB9415365A external-priority patent/GB9415365D0/en
Priority claimed from GB9415387A external-priority patent/GB9415387D0/en
Application filed by Discovision Ass filed Critical Discovision Ass
Application granted granted Critical
Publication of ATE278988T1 publication Critical patent/ATE278988T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Television Systems (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Debugging And Monitoring (AREA)
AT00201754T 1994-03-24 1995-02-28 Verfahren und vorrichtung zur schnittstellenbildung mit ram-speicher ATE278988T1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB9405914A GB9405914D0 (en) 1994-03-24 1994-03-24 Video decompression
GB9415413A GB9415413D0 (en) 1994-07-29 1994-07-29 Method and apparatus for video decompression
GB9415391A GB9415391D0 (en) 1994-07-29 1994-07-29 Method for accessing banks of dram
GB9415365A GB9415365D0 (en) 1994-07-29 1994-07-29 Method for accessing ram
GB9415387A GB9415387D0 (en) 1994-07-29 1994-07-29 Method and apparatus for addressing memory

Publications (1)

Publication Number Publication Date
ATE278988T1 true ATE278988T1 (de) 2004-10-15

Family

ID=27517237

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00201754T ATE278988T1 (de) 1994-03-24 1995-02-28 Verfahren und vorrichtung zur schnittstellenbildung mit ram-speicher

Country Status (3)

Country Link
EP (6) EP1026600B1 (de)
AT (1) ATE278988T1 (de)
DE (1) DE69533630T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336180B1 (en) 1997-04-30 2002-01-01 Canon Kabushiki Kaisha Method, apparatus and system for managing virtual memory with virtual-physical mapping
US5828907A (en) * 1992-06-30 1998-10-27 Discovision Associates Token-based adaptive video processing arrangement
EP0793390A3 (de) * 1996-02-28 1999-11-03 Koninklijke Philips Electronics N.V. MPEG-Signaldekodierungsvorrichtung
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
US6195674B1 (en) 1997-04-30 2001-02-27 Canon Kabushiki Kaisha Fast DCT apparatus
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6259456B1 (en) 1997-04-30 2001-07-10 Canon Kabushiki Kaisha Data normalization techniques
US6414687B1 (en) 1997-04-30 2002-07-02 Canon Kabushiki Kaisha Register setting-micro programming system
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
FR2766937B1 (fr) * 1997-07-31 2001-04-27 Sqware T Protocole et systeme de liaison par bus entre elements d'un microcontroleur
JP2000010863A (ja) * 1998-06-24 2000-01-14 Sony Computer Entertainment Inc 情報処理装置および方法、並びに提供媒体
US6851052B1 (en) * 1998-12-10 2005-02-01 Telcordia Technologies, Inc. Method and device for generating approximate message authentication codes
US7212440B2 (en) 2004-12-30 2007-05-01 Sandisk Corporation On-chip data grouping and alignment

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0576749B1 (de) * 1992-06-30 1999-06-02 Discovision Associates Datenpipelinesystem
JPS53114617A (en) * 1977-03-17 1978-10-06 Toshiba Corp Memory unit for picture processing
US4135242A (en) * 1977-11-07 1979-01-16 Ncr Corporation Method and processor having bit-addressable scratch pad memory
GB2039106B (en) * 1979-01-02 1983-03-23 Honeywell Inf Systems Number format conversion in computer
US4564915A (en) * 1980-04-11 1986-01-14 Ampex Corporation YIQ Computer graphics system
DE3138897A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur verarbeitung von speicheroperanden fuer dezimale und logische befehle
US4800431A (en) * 1984-03-19 1989-01-24 Schlumberger Systems And Services, Inc. Video stream processing frame buffer controller
JPS6180940A (ja) * 1984-09-28 1986-04-24 Hitachi Ltd デ−タ伝送方式
JP2520404B2 (ja) * 1986-11-10 1996-07-31 日本電気株式会社 圧縮復号化装置
EP0321628B1 (de) * 1987-12-23 1992-11-04 International Business Machines Corporation Gemeinsam genutzte Speicherschnittstelle für Datenverarbeitungsanlage
FR2651402B1 (fr) * 1989-08-22 1991-10-25 Europ Rech Electr Lab Dispositif de conversion de frequence trame et du nombre de lignes pour un recepteur de television haute definition.
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리
US5231605A (en) * 1991-01-31 1993-07-27 Micron Technology, Inc. DRAM compressed data test mode with expected data
US5265212A (en) * 1992-04-01 1993-11-23 Digital Equipment Corporation Sharing of bus access among multiple state machines with minimal wait time and prioritization of like cycle types
US5289577A (en) * 1992-06-04 1994-02-22 International Business Machines Incorporated Process-pipeline architecture for image/video processing

Also Published As

Publication number Publication date
EP0895422A3 (de) 1999-03-10
EP0674266A2 (de) 1995-09-27
DE69533630D1 (de) 2004-11-11
EP0895167A2 (de) 1999-02-03
DE69533630T2 (de) 2005-02-24
EP1026600A2 (de) 2000-08-09
EP1026600B1 (de) 2004-10-06
EP0895161A3 (de) 1999-02-10
EP0895167A3 (de) 1999-03-10
EP0895161A2 (de) 1999-02-03
EP0895422A2 (de) 1999-02-03
EP1026600A3 (de) 2000-11-08
EP0895166A3 (de) 1999-03-10
EP0895166A2 (de) 1999-02-03
EP0674266A3 (de) 1997-12-03

Similar Documents

Publication Publication Date Title
ATE278988T1 (de) Verfahren und vorrichtung zur schnittstellenbildung mit ram-speicher
KR960006379A (ko) 신호 수신 장치
KR920001350A (ko) 메시지 송수신에 이용되는 번지 정보 관리 방법 및 그 장치
KR920019131A (ko) 통신방식과 시스템제어방식
CN105677598B (zh) 基于i2c接口快速读取多个mems传感器数据的模块和方法
EP0971292A3 (de) Verfahren und Vorrichtung zur Übertragung von Daten über einen Prozessorschnittstellenbus
EP2239741A3 (de) Übertragungssystem, -verfahren und Übertragungs-/Empfangssystem
NL1009451A1 (nl) Serieël interface-circuit en een daarvan gebruikmakende signaalverwerkingswerkwijze.
JPS6361533A (ja) シリアルデ−タ転送装置
EP0228954A1 (de) Wahlmodul für Telephonleitungsschnittstelle
US6925505B2 (en) Method and device for data transmission control between IDE apparatuses
EP1282264A3 (de) Verfahren und Vorrichtung zur Mehrfachsendung
KR0143684B1 (ko) I2c 프로토콜 지원용 인터페이스
EP0903900A3 (de) Bitübertragungsschicht-Schnittstelle und Verfahren zur Arbitrierung über einen seriellen Bus unter Verwendung von Zustandssignalen der digitalen Leitung
EP0903900A9 (de) Bitübertragungsschicht-Schnittstelle und Verfahren zur Arbitrierung über einen seriellen Bus unter Verwendung von Zustandssignalen der digitalen Leitung
CN107453832B (zh) 一种pcm接口主从模式自适应方法、可编程逻辑器件和系统
JP2501450B2 (ja) ゲ−トウエイ
JP3193942B2 (ja) データ収集伝送装置
ES2002316A6 (es) Procedimiento y disposicion de conexion para transmitir senales de datos entre dos equipos de control pertenecientes a un sistema de lineas en anillo
KR100262263B1 (ko) 전전자 교환기에서 프로세서와 디바이스간의 버스 운용방법
JPS62285551A (ja) デ−タ伝送装置
JPS61142831A (ja) 多重集配信装置
KR950025541A (ko) 브이엠이(vme)를 에스버스(sbus)로 데이타 전송을 위한 사이즈 정보 발생회로
JP3675724B2 (ja) セル遅延削減方法及びセル遅延削減システム
JP2544511B2 (ja) 高能率ディジタル多重装置の伝送方式

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties